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hynix semiconductor inc. 8-bit single-chip microcontrollers gms81c7008 GMS81C7016 users manual (ver. 2.01)
version 2.01 published by mcu application team 2001 hynix semiconductor inc. all right reserved. additional information of this manual may be served by hynix semiconductor offices in korea or distributors and representatives listed at address directory. hynix semiconductor reserves the right to make changes to any information here in at any time without notice. the information, diagrams and other data in this manual are correct and reliable; however, hynix semiconductor is in no way res ponsible for any violations of patents or other rights of the third party generated by the use of this manual. revision history version 2.01 (apr., 2001) this book delete product of 52sdip package also, no longer produce 52pin mcu. the compay name hyundai electronics industires co., ltd. changed to hynix semiconductor inc. version 2.00 (feb., 2001) delete product of 52lqfp package. fixed some errata that pin number 25 and 26 on 52sdip package are reversed. version 1.02 (nov., 2000) fixed the name of lcr register on page 39 and 75, the bur register on page 66. version 1.01 (sep., 2000) sticker correct the bit lvde of lvdr register on page 91.
gms81c7008/7016/7108/7116 apr., 2001 ver 2.01 table of contents 1. overview............................................1 description .........................................................1 features .............................................................1 development tools ............................................2 ordering information ..........................................2 2. block diagram .................................3 3. pin assignment ................................4 4. package dimension ........................5 5. pin function......................................6 6. port structures............................9 7. electrical characteristics ....11 absolute maximum ratings .............................11 recommended operating conditions ..............11 dc electrical characteristics ...........................11 a/d converter characteristics .........................13 ac characteristics ...........................................13 serial interface timing characteristics ............15 typical characteristics .....................................16 8. memory organization.................18 registers ..........................................................18 program memory .............................................21 data memory ...................................................24 list of control registers ...................................25 addressing mode .............................................28 9. i/o ports ...........................................32 registers for port .............................................32 i/o ports configuration ....................................33 10. clock generator .......................37 11. operation mode ..........................39 operation mode switching ...............................40 12. basic interval timer..................42 13. timer/event counter ................44 8-bit timer / counter mode ..............................47 16-bit timer / counter mode ............................51 8-bit capture mode ..........................................52 16-bit capture mode ........................................53 timer output port mode ....................................53 pwm mode ......................................................54 14. analog digital converter .....57 15. serial communication ..............59 transmission/receiving timing ...................... 60 the method of serial i/o ................................. 61 the method to test correct transmission ...... 61 16. buzzer function .........................62 17. interrupts ....................................64 interrupt sequence .......................................... 66 brk interrupt .................................................. 67 multi interrupt .................................................. 67 external interrupt ............................................. 68 key scan interrupt .......................................... 68 18. lcd driver .....................................70 lcd control registers .................................... 70 duty and bias selection of lcd driver ............ 72 selecting frame frequency ............................ 72 lcd display memory ...................................... 75 control method of lcd driver ......................... 76 19. watch / watchdog timer .........78 watch timer .................................................... 78 watchdog timer .............................................. 78 20. power down operation...........81 sleep mode ................................................... 81 stop mode .................................................... 82 21. oscillator circuit.....................85 22. reset ...............................................86 external reset input ........................................ 86 watchdog timer reset ................................... 86 23. power fail processor.............87 24. development tools...................89 otp programming .......................................... 89 emulator eva. board setting .......................... 90 appendix a. mask order sheet .......................... i b. instruction ...................................... ii terminology list .................................................ii instruction map .................................................. iii
gms81c7008/7016/7108/7116 apr., 2001 ver 2.01 instruction set ................................................... iv c. software example ........................ x
gms81c7008/7016 apr., 2001 ver 2.01 1 gms81c7008/16 cmos single-chip 8-bit microcontroller with lcd driver & a/d converter 1. overview 1.1 description the gms81c7008/7016 is advanced cmos 8-bit microcontrollers with 8k/16k bytes of rom. there are a powerful microcontroller which provides a highly flexible and cost effective solution to many lcd applications. these provide the following standard fea tures:16k/ 8k bytes of mask type rom or 16k bytes otp rom, 448 bytes of ram, 8-bit timer/counter, 8-bit a/d converter, 10 bit high speed p wm output, programmable buzzer driving port, 8-bit basic interval timer, watch dog timer, serial peripheral interface, on chip osc illator and clock circuitry. they also come with 4com/24seg lcd driver. in addition, it support power saving mode to reduce power consumpti on. 1.2 features ? 8k/16k bytes on-chip programmable rom ? 448 bytes of on-chip data ram (included stack area and 27 nibbles lcd display ram) ? instruction execution time 1 m s at 4mhz (2cycle nop instruction) ? one 8-bit basic interval timer ? one watch timer ? one watchdog timer ? four 8-bit timer/event counter (or two 16-bit timer/event counter) ? two channel 10-bit high speed pwm output ? three external interrupt input ports ? one programmable 6-bit buzzer driving port - 500hz ~ 250khz@4mhz ? 49 i/o ports ? eight channel 8-bit a/d converter ? one 8-bit serial communication interface ? lcd display/ controller - static mode (27seg x 1com, static) - 1/2 duty mode (26seg x 2com, 1/2 or 1/3 bias) - 1/3 duty mode (25seg x 3com, 1/3 bias) - 1/4 duty mode (24seg x 4com, 1/3 bias) - internal built-in resistor circuit for bias ? thirteen interrupt sources - basic interval timer: 1 - external input: 3 - timer/event counter: 4 - adc: 1 - serial interface: 1 - wt:1 - wdt: 1 - key scan: 1 ? main clock oscillation (1.0~4.5mhz) - crystal - ceramic resonator - external r oscillator (built-in capacitor) ? sub clock oscillation - 32.768khz crystal oscillator ? power saving operation mode - main / sub active mode changeable - 2/8/16/64 divided system clock selectable ? power down mode - stop mode - sleep mode - sub active mode ? 2.7v to 5.5v wide operating voltage range ? noise immunity circuit for ems device name rom size ram size i/o otp package gms81c7008 8k bytes 448 bytes 49 gms87c7016 64sdip, 64mqfp GMS81C7016 16k bytes 448 bytes 49 gms87c7016
gms81c7008/7016 2 apr., 2001 ver 2.01 - power fail processor - built in noise filter ? 64sdip, 64lqfp package types ? available 16k bytes otp version 1.3 development tools note: there are several setting switches in the emulator. user should read carefully and do setting properly before developing the program refer to "24.2 emulator eva. board setting" on page 90. otherwise, the emulator may not work properly. the gms81c7008/16 is supported by a full-featured macro as- sembler, an in-circuit emulator choice-dr. tm and otp pro- grammers. there are two different type programmers, one is single type, another is gang type. for more detail, refer to otp programming chapter. macro assembler operates under the ms- windows 95/98 tm . please contact sales part of hynix semiconductor. 1.4 ordering information software - ms- window base assembler - linker / editor / debugger hardware (emulator) - choice-dr. - choice-dr. eva 81c51/81c7x b/d otp program- mer - choice-sigma (single type) - choice-gang4 (4-gang type) device name rom size (bytes) ram size package mask rom version gms81c7008 k GMS81C7016 k gms81c7008 q GMS81C7016 q 8k bytes 16k bytes 8k bytes 16k bytes 448 bytes 448 bytes 448 bytes 448 bytes 64sdip 64sdip 64mqfp 64mqfp otp rom version gms87c7016 k gms87c7016 q 16k bytes otp 16k bytes otp 448 bytes 448 bytes 64sdip 64mqfp
gms81c7008/7016 apr., 2001 ver 2.01 3 2. block diagram gms81c7008/7016 alu lcd controller / driver (lcdc) accumulator stack pointer interrupt controller data memory lcd display memory program memory data table pc 8-bit basic interval timer high speed pc r1 r0 r3 buzzer driver psw system controller timing generator system clock controller clock generator high freq. low freq. reset xin xout sxin sxout common drive output com0 r00 / int0 r01 / int1 r02 / int2 r03 / ec0 r04 / ec2 r05 / sck r06 / so r07 / si r10 r11 r30 / buz vdd vss power supply vcl0 vcl1 vcl2 com1/seg26 com2/seg25 com3/seg24 lcd power control circuit avdd avss power supply circuit bias r20 / an0 r31 / pwm0 / t1o r32 / pwm1 / t3o r33 r21 / an1 r22 / an2 r23 / an3 8-bit a/d converter r2 pwm 8-bit timer/counter sio r24 / an4 r25 / an5 r26 / an6 r27 / an7 r4 r5 r6 r34 / wdto watch/ timer r35 / sxout r36 / sxin segment drive output seg0 ~ seg23 r40-r47 watchdog key scan r50-r56 r60-r67 lcd power supply
gms81c7008/7016 4 apr., 2001 ver 2.01 3. pin assignment vcl0 vcl1 vcl2 av dd r20 r21 r22 r23 av ss bias x in x out reset r36 r35 v ss an0 an1 an2 an3 pwm1 / t3o pwm0 / t1o buz wdto r24 r25 r26 r27 r07 r06 r05 r04 r03 r02 r01 r00 r11 r10 r34 r33 si so ec2 ec0 int2 int1 int0 v dd com3 com2 com1 com0 r67 r66 r65 r64 r63 r62 r61 r60 r57 r56 r55 r54 r53 r52 r51 r50 r47 r46 r45 r44 r43 r42 r41 r40 r30 r31 r32 r21 r66 r67 com0 com1 com2 com3 v dd vcl0 vcl1 vcl2 av dd r20 an1 seg22 r02 r42 r41 r40 r30 r31 r32 r33 r34 r10 r11 r00 r01 int2 int0 int1 r65 r63 r62 r61 r60 r57 r56 r55 r54 r53 r52 r51 r50 r47 r46 r45 r64 r44 r43 r22 av ss bias xin xout reset r36 r35 v ss r24 r25 r26 r27 r07 r06 r05 r23 r04 r03 an2 sx in sx out an4 an5 an6 an7 si so sck an3 ec2 ec0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 51 50 49 32 31 30 29 28 27 26 25 24 23 22 21 20 52 53 54 55 56 57 58 59 60 61 62 63 64 64mqfp 64sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 gms81c7008/7016 gms81c7008/7016 (top view) (top view) an4 an5 an6 an7 sx in sx out sck seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg26 seg25 seg24 wdto pwm1/t3o pwm0/t1o buz seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg23 an0 seg26 seg25 seg24 ks1 ks0 ks0 ks1
gms81c7008/7016 apr., 2001 ver 2.01 5 4. package dimension unit: inch 2.280 2.260 0.022 0.016 0.050 0.030 0.070 typ. 0.140 0.120 min. 0.015 0.680 0.660 0.750 typ. 0-15 64sdip 0 .0 1 2 0 .0 0 8 0.205 max. 20.10 19.90 24.15 23.65 18.15 17.65 14.10 13.90 3.18 max. 0.50 0.35 1.00 typ. see detail a 1.03 0.73 0-7 0.36 0.10 0.23 0.13 1.95 ref detail a unit: mm 64mqfp
gms81c7008/7016 6 apr., 2001 ver 2.01 5. pin function v dd : supply voltage. v ss : circuit ground. reset : reset the mcu. av dd : supply voltage to the ladder resistor of adc circuit. to enhance the resolution of analog to digital converter, use inde- pendent power source as well as possible, other than digital pow- er source. av ss : adc circuit ground. x in : input to the inverting oscillator amplifier and input to the in- ternal main clock operating circuit. x out : output from the inverting oscillator amplifier. bias : lcd bias voltage input pin. vcl0~vcl2 : lcd driver power supply pins. the voltage on each pin is vcl2 > vcl1 > vcl0. for details, refer to 18. lcd driver on page 70. com0~com3 : lcd common signal output pins. also, the pins of com1,com2 and com3 are shared with lcd segment sig- nal outputs of seg26, seg25, seg24 as application require- ment. sx in : input to the internal subsystem clock operating circuit. in addition, sx in is shared with the r36 which is selected by the software option. sx out : output from the inverting subsystem oscillator amplifi- er. in addition, sx out is shared with the r35 which is selected by the software option. r00~r07: r0 is an 8-bit cmos bidirectional i/o port. r0 pins 1 or 0 written to the port direction register can be used as outputs or schmitt trigger inputs. also, pull-up resistors and open-drain outputs are software assignable. in addition, r0 serves the functions of the various following spe- cial features. r10~r11 : r1 is a 2-bit cmos bidirectional i/o port. r1 pins 1 or 0 written to the port direction register can be used as outputs or inputs. also, pull-up resistors and open-drain outputs are soft- ware assignable. these pins are not served on 81c71xx. in addition, r0 serves the functions of the various following spe- cial features. r20~r27 : r2 is an 8-bit cmos bidirectional i/o port. r2 pins 1 or 0 written to the port direction register can be used as outputs or inputs. also, pull-up resistors and open-drain outputs are soft- ware assignable.r24~r27 are not served on 81c71xx. in addition, r2 is shared with the adc input. r30~r36 : r3 is a 7-bit cmos bidirectional i/o port. r3 pins 1 or 0 written to the port direction register can be used as outputs or inputs. also, pull-up resistors and open-drain outputs are soft- ware assignable. r33, r34 are not served on 81c71xx. in addition, r3 serves the functions of the various follow- ing special features. seg0~seg7 : these pins generate lcd segment signal output. every lcd segment pins are shared with normal r4 input/output port. r4 is an 8-bit cmos bidirectional i/o port. r4 pins 1 or 0 written to the port direction register can be used as outputs or in- port pin alternate function r00 r01 r02 r03 r04 r05 r06 r07 int0 (external interrupt 0) int1 (external interrupt 1) int2 (external interrupt 2) ec0 (event counter input 0) ec2 (event counter input 2) sck (serial clock) so (serial data output) si (serial data input) port pin alternate function r00 r01 ks0 (key scan 0) ks1 (key scan 1) port pin alternate function r20 r21 r22 r23 r24 r25 r26 r27 an0 (analog input 0) an1 (analog input 1) an2 (analog input 2) an3 (analog input 3) an4 (analog input 4) an5 (analog input 5) an6 (analog input 6) an7 (analog input 7) port pin alternate function r30 r31 r32 r33 r34 r35 r36 buz (buzzer driving output) pwm0 / t1o (pwm 0 output / timer 1 output) pwm1 /t3o (pwm 1 output / timer 3 output) - wdto (watchdog timer output) sx out (sub clock output) sx in (sub clock input)
gms81c7008/7016 apr., 2001 ver 2.01 7 puts. seg8~seg15 : these pins generate lcd segment signal output. every lcd segment pins are shared with normal r5 input/output port. r5 is an 8-bit cmos bidirectional i/o port. r5 pins 1 or 0 written to the port direction register can be used as outputs or in- puts. seg16~seg23 : these pins generate lcd segment signal out- put. every lcd segment pins are shared with normal r6 input/output port. r6 is an 8-bit cmos bidirectional i/o port. r6 pins 1 or 0 written to the port direction register can be used as outputs or in- puts. lcd pin function port pin seg0 (lcd segment 0 signal output) seg1 (lcd segment 1 signal output) seg2 (lcd segment 2 signal output) seg3 (lcd segment 3 signal output) seg4 (lcd segment 4 signal output) seg5 (lcd segment 5 signal output) seg6 (lcd segment 6 signal output) seg7 (lcd segment 7 signal output) r40 r41 r42 r43 r44 r45 r46 r47 lcd pin function port pin seg8 (lcd segment 8 signal output) seg9 (lcd segment 9 signal output) seg10 (lcd segment 10 signal output) seg11 (lcd segment 11 signal output) seg12 (lcd segment 12 signal output) seg13 (lcd segment 13 signal output) seg14 (lcd segment 14 signal output) seg15 (lcd segment 15 signal output) r50 r51 r52 r53 r54 r55 r56 r57 lcd pin function port pin seg16 (lcd segment 16 signal output) seg17 (lcd segment 17 signal output) seg18 (lcd segment 18 signal output) seg19 (lcd segment 19 signal output) seg20 (lcd segment 20 signal output) seg21 (lcd segment 21 signal output) seg22 (lcd segment 22 signal output) seg23 (lcd segment 23 signal output) r60 r61 r62 r63 r64 r65 r66 r67
gms81c7008/7016 8 apr., 2001 ver 2.01 pin name (alternate) in/out (alternate) function basic alternate v dd - supply voltage v ss - circuit ground reset i reset signal input av dd - supply voltage input pin for adc av ss - ground level input pin for adc x in i oscillation input x out o oscillation output bias i lcd bias voltage input vcl0~vcl2 i lcd driver power supply com0 o lcd common signal output com1(seg26) o(o) lcd common signal output lcd segment signal output com2(seg25) o(o) com3(seg24) o(o) r00 (int0) i/o (i) 8-bit general i/o ports external interrupt 0 input r01 (int1) i/o (i) external interrupt 1 input r02 (int2) i/o (i) external interrupt 2 input r03 (ec0) i/o (i) timer/counter 0 external input r04 (ec2) i/o (i) timer/counter 1 external input r05 (sck) i/o (i/o) serial clock i/o r06 (so) i/o (o) serial data output r07 (si) i/o (i) serial data input r10, r11(ks0 , ks1 ) i/o (i) 2-bit general i/o ports key scan input r20~r27(an0~an7) i/o(i) 8-bit general i/o ports analog voltage input r30(buz) i/o(o) 7-bit general i/o ports buzzer driving output r31(pwm0 / t1o) i/o(o) pwm 0 output / timer 1 output r32(pwm1 / t3o) i/o(o) pwm 1 output / timer 2 output r33 i/o - r34(wdto ) i/o(o) watchdog timer output r35(sx out ) i/o(o) sub clock output r36(sx in ) i/o(i) sub clock input seg0 ~ seg7 (r40~r47) o (i/o) lcd segment signal output 8-bit general i/o ports seg8 ~ seg15 (r50~r57) o (i/o) lcd segment signal output 8-bit general i/o ports seg16 ~ seg23 (r60~r67) o (i/o) lcd segment signal output 8-bit general i/o ports table 5-1 port function description
gms81c7008/7016 apr., 2001 ver 2.01 9 6. port structures r00/int0, r01/int1, r02/int2, r03/ec0, r04/ec2, r05/sck, r07/s r30/buz, r31/pwm0/t1o, r32/pwm1/t3o, r34/wdto , r06 r20/an0~r27/an7 r10~r11, r33, r35, r36 reset sxin, sxout pin data reg. dir. reg. noise canceller int0 ~ int2 pull up reg. mux rd v dd v ss pull-up tr. ec0,ec2 open drain reg. data bus si,sck tr.: transistor reg.: register pin data reg. dir. reg. pull up reg. mux v dd v ss pull-up tr. open drain reg. buz,so,wdto data bus pwm0,pwm1 rd pin data reg. dir. reg. analog switch an0 ~ an7 pull up reg. mux rd v dd v ss pull-up tr. open drain reg. data bus pin data reg. dir. reg. pull up reg. mux rd v dd v ss pull-up tr. open drain reg. data bus reset v ss noise canceller internal reset v ss v dd high voltage on(otp) v dd otp mcu :disconnected mask mcu :connected otp mcu :connected mask mcu :disconnected sxout v ss internal sxin sub clock off (r35) (r36) v dd system clock lcr.7=0
gms81c7008/7016 10 apr., 2001 ver 2.01 r40~r47, r50~r57, r60~r67 / seg0~seg23 com0~com3 / seg24~seg26 xin, xout pin data reg. dir. reg. mux rd v dd v ss data bus vcl2 vcl1 v ss vcl0 lcd data vcl2 enable lcd data vcl1 enable lcd data vcl0 enable lcd data gnd enable pin vcl2 vcl1 v ss vcl0 lcd data vcl2 enable lcd data vcl1 enable lcd data vcl0 enable lcd data gnd enable xout v dd v ss main clock xin stop & main clock off
gms81c7008/7016 apr., 2001 ver 2.01 11 7. electrical characteristics 7.1 absolute maximum ratings supply voltage ........................................... -0.3 to +6.0 v storage temperature ................................-40 to +125 c voltage on any pin with respect to ground (v ss ) ............................................................... -0.3 to v dd +0.3 maximum current out of v ss pin ........................100 ma maximum current into v dd pin ............................80 ma maximum current sunk by (i ol per i/o pin) ........20 ma maximum output current sourced by (i oh per i/o pin) ...............................................................................15 ma maximum current ( s i ol ) .................................... 100 ma maximum current ( s i oh )...................................... 60 ma note: stresses above those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 7.2 recommended operating conditions 7.3 dc electrical characteristics (t a =-20~85 c, v dd =2.7~5.5v) , parameter symbol condition specifications unit min. max. supply voltage v dd f xin =4.19mhz f sxin =32.768khz 2.7 5.5 v operating frequency f xin v dd =2.7~5.5v 14.5mhz sub operating frequency f sxin v dd =2.7~5.5v 30 35 khz operating temperature t opr -20 +85 c parameter symbol condition specifications unit min. typ. max. input high voltage v ih1 reset , r0 (except r06) 0.8 v dd - v dd v v ih2 other pins 0.7 v dd - v dd v input low voltage v il1 reset , r0 (except r06) 0 - 0.2 v dd v v il2 other pins 0 - 0.3 v dd v output high voltage v oh1 r0,r1,r2,r3 i oh1 =-0.5ma v dd -0.1 --v v oh2 seg, com i oh2 =-30 m a--0.4v output low voltage v ol1 r0,r1,r2,r3 i ol1 =0.4ma - - 0.2 v v ol2 seg, com i ol2 =30 m a v dd -0.2 --v input high leakage current i ih1 v in =v dd , all input pins except x in , sx in --1 m a i ih2 v in =v dd, x in , sx in --20 m a
gms81c7008/7016 12 apr., 2001 ver 2.01 input low leakage current i il1 v in =0, all input pins except x in , sx in ---1 m a i il2 v in =0 , x in , sx in - - -20 m a pull-up resistor 1 r port v in =0v, v dd =5.5v, r0, r1, r2 60 160 350 k w lcd voltage dividing resistor r lcd v dd =5.5v 456585k w voltage drop |v dd -com n | , n =0~3 v dc v dd =2.7 ~ 5.5v -15 m a per common pin --120mv voltage drop |v dd -seg n | , n =0~26 v ds v dd =2.7 ~ 5.5v -15 m a per segment pin --120mv v cl2 output voltage v cl2 v dd =2.7 ~ 5.5v, 1/3 bias bias pin and vcl2 pin are shorted v dd -0.3 v dd v dd +0.3 v v cl1 output voltage v cl1 0.66v dd -0.2 0.66v dd 0.66v dd +0.3 v cl0 output voltage v cl0 0.33v dd -0.3 0.33v dd 0.33v dd +0.3 rc oscillation fre- quency f rc r=60k w , v dd = 5v 123mhz supply current 1 ( ) means at 3v opera- tion i dd1 main clock operation mode 2 v dd =5.5v 10%, x in =4mhz, s xin =32khz - 2.9 (1.3) 7.0 (3.0) ma i dd2 sleep mode (main active) 3 v dd =5.5v 10%, x in =4mhz, s xin =32khz - 0.4 (0.1) 1.7 (1.0) ma i dd3 stop mode 2 v dd =5v 10%, x in = 0hz, s xin = 32khz 2.0 (1.0) 12 (5) m a i dd4 sub clock operation mode 4 v dd =5.5v 10%, x in =0hz, s xin =32khz - 350 (70) 500 (200) m a i dd5 sleep mode (sub active) 5 v dd =3v 10%, x in = 0hz, s xin = 32khz - 10 (3) 50 (20) m a i dd6 stop mode 4 v dd =5v 10%, x in = 0hz, s xin = 0hz s xin , sxout are used as r35, r36. - 1.0 (0.5) 12 (5) m a 1. supply current in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors , comparator volt- age divide resistor, lvd circuit and output port drive currents. 2. this mode set system clock mode register(scmr) to xxxx0000 b that is f xin /2 3. this mode set scmr to xxxx0000 b (f xin /2) and set smr to 1. 4. main-frequency clock stops and sub-frequency clock in not used and set scmr to xxxx0011 b . 5. main-frequency clock stops and sub-frequency clock in not used, set scmr to xxxx0011 b and set smr to 1. parameter symbol condition specifications unit min. typ. max.
gms81c7008/7016 apr., 2001 ver 2.01 13 7.4 a/d converter characteristics (t a =25 c, v ss =0v, v dd =5.0v, av dd =5.0v @f xin =4mhz) 7.5 ac characteristics (t a =-20~+85 c, v dd =5v 10% , v ss =0v) parameter symbol test condition specifications unit min. typ. 1 1. data in typ column is at 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. max. analog input voltage range v ain v dd =av dd =5.0v v ss -0.3 - av dd +0.3 v non-linearity error n nle - 1.0 1.5 lsb differential non-linearity error n dnle - 1.0 1.5 lsb zero offset error n zoe - 0.5 1.5 lsb full scale error n fse - 0.25 0.5 lsb gain error n ge - 1.0 1.5 lsb overall accuracy n acc - 1.0 1.5 lsb av dd input current i ref - - 200 m a conversion time t conv --20 m s analog power supply input range av dd v dd =5.0v v dd =3.0v 3.0 2.7 - v dd v parameter symbol pins specifications unit min. typ. max. operating frequency f main x in 0.455 - 4.2 mhz f sub sx in 30 32.768 35 khz external clock pulse width t mcpw x in 80 - - ns t scpw sx in 14.7 - - m s external clock transition time t mrcp, t mfcp x in - - 20 ns t srcp, t sfcp sx in --3 m s main oscillation stabilizing time t mst x in , x out at 4mhz --20ms sub oscillation stabilizing time t sst sx in , sx out -0.51 s interrupt pulse width t iw int0, int1, int2 2 - - t sys 1 reset input width t rst reset 8- -t sys 1 event counter input pulse width t ecw ec0, ec2 2 - - t sys 1 1. t sys is one of 2/f main or 8/f main or 16/f main or 64/f main in the main clock operation mode, t sys is one of 2/f sub or 8/f sub or 16/f sub or 64/f sub in the sub clock operation mode.
gms81c7008/7016 14 apr., 2001 ver 2.01 figure 7-1 timing chart t mrcp t mfcp x in int0, int1 int2 0.5v v dd -0.5v 0.2v dd 0.8v dd 0.2v dd reset 0.2v dd 0.8v dd ec0, ec2 t iw t iw t rst t ecw t ecw 1/f main t mcpw t mcpw t srcp t sfcp sx in 0.5v v dd -0.5v 1/f sub t scpw t scpw t sys
gms81c7008/7016 apr., 2001 ver 2.01 15 7.6 serial interface timing characteristics (t a =-20~+85 c, v dd =2.7~5.5v, v ss =0v, f xin =4mhz) figure 7-2 serial i/o timing chart parameter symbol pins specifications unit min. typ. max. serial input clock pulse t scyc sck 2t sys +200 -8ns serial input clock pulse width t sckw sck t sys +70 -8ns sin input setup time (external sck) t sus sin 100 - - ns sin input setup time (internal sck) t sus sin 200 - - ns sin input hold time t hs sin t sys +70 --ns serial output clock cycle time t scyc sck 4t sys - 16t sys ns serial output clock pulse width t sckw sck t sys -30 --ns serial output clock pulse transition time t fsck t rsck sck - - 30 ns serial output delay time s out so - - 100 ns sclk sin 0.2v dd sout 0.2v dd 0.8v dd t scyc t sckw t sckw t rsck t fsck 0.8v dd t sus t hs t ds 0.2v dd 0.8v dd
gms81c7008/7016 16 apr., 2001 ver 2.01 7.7 typical characteristics this graphs and tables provided in this section are for de- sign guidance only and are not tested or guaranteed. in some graphs or tables the data presented are out- side specified operating range (e.g. outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. typical represents the mean of the distribution while max or min represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation i ol - - - - v ol , v dd =5.5v 40 30 20 10 0 (ma) i ol v ol (v) i ol - - - - v ol , v dd =3.0v (ma) i ol 0.5 1.0 1.5 2.0 2.5 v ol (v) i oh - - - - v oh , v dd =5.0v -20 -15 -10 -5 0 (ma) i oh 12 345 v oh (v) i oh - - - - v oh , v dd =3.0v -8 -6 -4 -2 0 (ma) i oh 0.5 1.0 1.5 2.0 2.5 v oh (v) ta=25 c r0,r1,r2,r3 pin 200 100 0 (k w ) -20 04080 ta ( c) r 12 345 f xin =4mhz v dd - - - - v ih1 4 3 2 1 0 (v) v ih1 23 45 6 v dd (v) v dd - - - - v ih2 4 3 2 1 0 (v) v ih2 23 45 6 v dd (v) ta=25 c f xin =4mhz ta=25 c 1 r0 (except r06) r1~r6 pin 20 15 10 5 (include r06) f xin =4mhz v dd - - - - v ih3 4 3 2 1 0 (v) v ih1 23 45 6 v dd (v) ta=25 c 1 x in , sx in r = 6.2k w 4 3 2 1 0 (mhz) f xin 2345 6 v dd (v) ta=25 c r = 20k w r = 180k w r = 60k w f xin - - - - v dd ta=25 c ta=25 c ta=25 c r pu - - - - t a , v dd =5.0v
gms81c7008/7016 apr., 2001 ver 2.01 17 i stop ( ( ( ( i dd6 ) - - - - v dd stop mode i dd1 - - - - v dd 4 3 2 1 0 (ma) i dd 6 v dd (v) normal operation (main opr.) i dd4 - - - - v dd 400 300 200 100 0 ( m a) i dd 23 45 6 v dd (v) normal mode (sub opr.) i sleep (i dd5 ) - - - - v dd sleep mode (sub opr.) i sleep (i dd2 ) - - - - v dd f xin =4mhz v dd - - - - v il1 4 3 2 1 0 (v) v ih1 23 45 6 v dd (v) v dd - - - - v il2 4 3 2 1 0 (v) v ih2 23 45 6 v dd (v) ta=25 c f xin =4mhz ta=25 c 1 r0 (except r06) r1~r6 pin (include r06) f xin =4mhz v dd - - - - v il3 4 3 2 1 0 (v) v ih1 23 45 6 v dd (v) ta=25 c 1 x in , sx in 23 45 sleep mode (main opr.) f sxin =32khz ta=25 c 400 300 200 100 0 ( m a) i dd 23 45 6 v dd (v) 12 9 6 3 0 ( m a) i dd 23 45 6 v dd (v) f sxin =32khz ta=25 c i stop (i dd3 ) - - - - v dd stop mode 4 3 2 1 0 ( m a) i dd 23 45 6 v dd (v) f xin =0hz ta=25 c f xin =4mhz ta=25 c f xin =4mhz ta=25 c 4 3 2 1 0 ( m a) i dd 23 45 6 v dd (v) f sxin =0hz ta=25 c
gms81c7008/7016 18 apr., 2001 ver 2.01 8. memory organization the gms81c7008/16 has separate address spaces for program memory and data memory. program memory can only be read, not written to. it can be up to 8k/16k bytes of program memory. data memory can be read and written to up to 448 bytes including the stack area and the lcd display ram area. 8.1 registers this device has six registers that are the program counter (pc), a accumulator (a), two index registers (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 8-1 configuration of registers accumulator: the accumulator is the 8-bit general purpose reg- ister, used for data operation such as transfer, temporary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below. figure 8-2 configuration of ya 16-bit register x, y registers : in the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. these modes are extremely ef- fective for referencing subroutine tables and memory tables. the index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumula- tors. stack pointer : the stack pointer is an 8-bit register used for oc- currence interrupts and calling out subroutines. stack pointer identifies the location in the stack to be access (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in ex- cess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. the stack can be located at any position within 011b h to 01ff h of the internal data memory. the sp is not initialized by hard- ware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. nor- mally, the initial value of ff h is used. note: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp ldx #0ffh txsp ; sp ? ffh program counter : the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indi- cates the address of the next instruction to be executed. in reset state, the program counter has reset routine address (pc h :0ff h , pc l :0fe h ). program status word : the program status word (psw) con- tains several bits that reflect the current state of the cpu. the psw is described in figure 8-3. it contains the negative flag, the overflow flag, the break flag the half carry (for bcd opera- tion), the interrupt enable flag, the zero flag, and the carry flag. [carry flag c] this flag stores any carry or not borrow from the alu of cpu after an arithmetic operation and is also changed by the shift in- struction or rotate instruction. [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is 0 and is cleared by any other result. accumulator x register y register stack pointer program counter program status word x a sp y pcl psw pch two 8-bit registers can be used as a ya 16-bit register y a y a sp 01 h stack area (100 h ~ 1ff h ) bit 15 bit 0 87 hardware fixed 00 h ~ff h lcd display ram area is located in 100 h ~11a h , sp (stack pointer) could be in 00 h ~ff h . user must have concerning that stack data does not cross over lcd ram area.
gms81c7008/7016 apr., 2001 ver 2.01 19 figure 8-3 psw (program status word) register [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all interrupts are disabled when cleared to 0. this flag immediately becomes 0 when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector address. [direct page flag g] this flag assigns ram page for direct addressing mode. in the di- rect addressing mode, addressing area is from zero page 00 h to 0ff h when this flag is "0". if it is set to "1", addressing area is assigned by rpr register (address 0f3 h ). it is set by setg in- struction and cleared by clrg. when content of rpr is above 2, malfunction will be occurred. [overflow flag v] this flag is set to 1 when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction exceeds +127(7f h ) or - 128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. when the bit instruction is exe- cuted, bit 7 of memory is copied to this flag. n negative flag v g b h i z c msb lsb reset value: 00 h psw overflow flag brk flag carry flag receives zero flag interrupt enable flag carry out half carry flag receives carry out from bit 1 of addition operlands select direct page when g=1, page is selected to page 1 ram page instruction bit1 of rpr bit0 of rpr 0 page clrg x x 0 page setg 0 0 1 page setg 0 1 reserved setg 1 0 reserved setg 1 1
gms81c7008/7016 20 apr., 2001 ver 2.01 figure 8-4 stack operation at execution of a call/tcall/pcall pcl pch 01fc sp after execution sp before execution 01fd 01fd 01fe 01ff 01ff push down at acceptance of interrupt pcl pch 01fc 01fc 01fd 01fe 01ff 01ff push down psw at execution of ret instruction pcl pch 01fc 01ff 01fd 01fe 01ff 01fd pop up at execution of ret instruction pcl pch 01fc 01ff 01fe 01fe 01ff 01fc pop up psw 0100h 01ffh stack depth at execution of push instruction a 01fc 01fe 01fd 01fe 01ff 01ff push down sp after execution sp before execution push a (x,y,psw) at execution of pop instruction a 01fc 01ff 01fd 01fe 01ff 01fe pop up pop a (x,y,psw)
gms81c7008/7016 apr., 2001 ver 2.01 21 8.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this device has 8k/16k bytes program memory space only physically implemented. accessing a location above ffff h will cause a wrap-around to 0000 h . figure 8-5, shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in ad- dress fffe h and ffff h as shown in figure 8-6. as shown in figure 8-5, each area is assigned a fixed location in program memory. program memory area contains the user pro- gram. figure 8-5 program memory map page call (pcall) area contains subroutine program to reduce program byte length by using 2 bytes pcall instead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall ad- dress, where it commences the execution of the service routine. the table call service area spaces 2-byte for every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 8-7. example: usage of tcall the interrupt causes the cpu to jump to specific location, where it commences the execution of the service routine. the external interrupt 0, for example, is assigned to location 0fffa h . the in- terrupt service locations spaces 2-byte interval: 0fff8 h and 0fff9 h for external interrupt 1, 0fffa h and 0fffb h for exter- nal interrupt 0, etc. any area from 0ff00 h to 0ffff h , if it is not going to be used, its service location is available as general purpose program mem- ory. figure 8-6 interrupt vector area interrupt vector area c000 h feff h ff00 h ffc0 h ffdf h ffe0 h ffff h pcall area e000 h tcall area gms81c7008 8k rom GMS81C7016 16k rom 0ffe0 h e2 address vector area memory e4 e6 e8 ea ec ee f0 f2 f4 f6 f8 fa fc fe timer/counter 3 timer/counter 2 watch timer a/d converter - external interrupt 0 timer/counter 1 basic interval timer key scan reset watchdog timer serial peripheral interface - means reserved area. note: external interrupt 2 external interrupt 1 timer/counter 0 - -
gms81c7008/7016 22 apr., 2001 ver 2.01 figure 8-7 pcall and tcall memory area pcall ? ? ? ? rel 4f35 pcall 35h tcall ? ? ? ? n 4a tcall 4 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffff h pcall area (256 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df 4f ~ ~ ~ ~ next 35 0ff35 h 0ff00 h 0ffff h 11111111 11010110 01001010 pc: fh fh dh 6h 4a ~ ~ ~ ~ 25 0ffd6 h 0ff00 h 0ffff h d1 next 0ffd7 h 0d125 h reverse 1 2 3
gms81c7008/7016 apr., 2001 ver 2.01 23 example: the usage software example of vector address for GMS81C7016. org 0ffe0h dw timer3 ; timer-3 dw timer2 ; timer-2 dw watch_timer ; watch timer dw adc ; adc dw sio ; serial interface dw not_used ; - dw not_used ; - dw int2 ; int.2 dw timer1 ; timer-1 dw timer0 ; timer-0 dw int1 ; int.1 dw int0 ; int.0 dw wd_timer ; watchdog timer dw bit_timer ; basic interval timer dw keyscan ; key scan timer dw reset ; reset org 0c000h ; in case of 16k rom start address ; org 0e000h ; in case of 8k rom start address ;******************************************* ; main program * ;******************************************* ; reset: ldm scmr,#0 ;when main clock mode di ;disable all interrupts ldm wdtr,#0 ;disable watch dog timer ldm rpr,#1 clrg ldx #0 ram_clr: lda #0 ;ram clear(!0000h ~ !00bfh) sta {x}+ cmpx #0c0h bne ram_clr setg ldx #0 ram_clr1: lda #0 sta {x}+ cmpx #1bh ;display ram clear(!0100h ~ !011ah) bne ram_clr1 clrg ; ldx #0ffh ;stack pointer initialize txsp ; ldm r0, #0 ;normal port 0 ldm r0dd,#82h ;normal port direction ldm r0pu,#0 ;normal pull up : : : ldm tdr0,#250 ;8us x 250 = 2000us ldm tm0,#0000_1111b ;start timer0, 8us at 4mhz ldm irqh,#0 ldm irql,#0 ldm ienh,#0000_1110b ;enable int0, int1, timer0 ldm ienl,#0 ldm ieds,#15h ;select falling edge detect on int pin ldm pmr,#3h ;set external interrupt pin(int0, int1) ei ;enable master interrupt
gms81c7008/7016 24 apr., 2001 ver 2.01 8.3 data memory figure 8-8 shows the internal data memory space available. data memory is divided into four groups, a user ram, control regis- ters, stack, and lcd memory. figure 8-8 data memory map user memory the both gms81c7008/16 has 448 8 bits for the user memory (ram). there are two page internal ram. page is selected by g-flag and ram page selection register rpr. when g-flag is cleared to 0, always page 0 is selected regardless of rpr value. if g-flag is set to 1, page will be selected according to rpr value. figure 8-9 ram page configuration control registers the control registers are used by the cpu and peripheral function blocks for controlling the desired operation of the device. there- fore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and i/o ports. the control registers are in address range of 0c0 h to 0ff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in general return ran- dom data, and write accesses will have an indeterminate effect. more detailed informations of each register are explained in each peripheral section. note: write only registers can not be accessed by bit ma- nipulation instruction (set1, clr1). do not use read-mod- ify-write instruction. use byte manipulation instruction, for example ldm. example; to write at ckctlr ldm ckctlr,#09h ;divide ratio( ? 16) stack area the stack provides the area where the return address is saved be- fore a jump is performed during the processing routine at the ex- ecution of a subroutine call instruction or the acceptance of an interrupt. when returning from the processing routine, executing the sub- routine return instruction [ret] restores the contents of the pro- gram counter from the stack; executing the interrupt return instruction [reti] restores the contents of the program counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack location number for the next save. refer to figure 8-4 on page 20. user memory control registers or stack area 0000 h 00bf h 00c0 h 00ff h 0100 h 01ff h page0 user memory page1 lcd display ram (27 nibbles) 011a h 011b h (192 bytes) (229 bytes) page 0 page 0: 00~ff h page 1 page 1: 100~1ff h rpr=1, g=1 g=0
gms81c7008/7016 apr., 2001 ver 2.01 25 8.4 list of control registers address register name symbol r/w initial value page 76543210 00c0 r0 port data register r0 r/w 0 0 0 0 0 0 0 0 page 33 00c1 r1 port data register r1 r/w - - - - - - 0 0 page 33 00c2 r2 port data register r2 r/w 0 0 0 0 0 0 0 0 page 33 00c3 r3 port data register r3 r/w - 0 0 0 0 0 0 0 page 33 00c4 r4 port data register r4 r/w 0 0 0 0 0 0 0 0 page 34 00c5 r5 port data register r5 r/w 0 0 0 0 0 0 0 0 page 34 00c6 r6 port data register r6 r/w 0 0 0 0 0 0 0 0 page 35 00c8 r0 port i/o direction register r0dd w 0 0 0 0 0 0 0 0 page 35 00c9 r1 port i/o direction register r1dd w - - - - - - 0 0 page 36 00ca r2 port i/o direction register r2dd w 0 0 0 0 0 0 0 0 page 36 00cb r3 port i/o direction register r3dd w - 0 0 0 0 0 0 0 page 35 00cc r4 port i/o direction register r4dd w 0 0 0 0 0 0 0 0 page 36 00cd r5 port i/o direction register r5dd w 0 0 0 0 0 0 0 0 page 36 00ce r6 port i/o direction register r6dd w 0 0 0 0 0 0 0 0 page 36 00d0 r0 port pull-up register r0pu w 0 0 0 0 0 0 0 0 page 33 00d1 r1 port pull-up register r1pu w - - - - - - 0 0 page 33 00d2 r2 port pull-up register r2pu w 0 0 0 0 0 0 0 0 page 33 00d3 r3 port pull-up register r3pu w - 0 0 0 0 0 0 0 page 33 00d4 r0 port open drain control register r0cr w 0 0 0 0 0 0 0 0 page 33 00d5 r1 port open drain control register r1cr w - - - - - - 0 0 page 33 00d6 r2 port open drain control register r2cr w 0 0 0 0 0 0 0 0 page 33 00d7 r3 port open drain control register r3cr w - 0 0 0 0 0 0 0 page 33 00d8 ext. interrupt edge selection register ieds r/w - - 0 0 0 0 0 0 page 69 00d9 port mode register pmr r/w 0 0 0 0 0 0 0 0 page 62, page 69 00da interrupt enable lower byte register ienl r/w 0 - - 0 0 0 0 0 page 65 00db interrupt enable upper byte register ienh r/w - 0 0 0 0 0 0 0 page 65 00dc interrupt request flag lower byte register irql r/w 0 - - 0 0 0 0 0 page 64 00dd interrupt request flag upper byte register irqh r/w - 0 0 0 0 0 0 0 page 64 00de sleep mode register smr w - - - - - - - 0 page 81 00df watch dog timer register wdtr r/w - - 0 1 0 0 1 0 page 79 00e0 timer0 mode register tm0 r/w - - 0 0 0 0 0 0 page 45 00e1 timer0 counter register t0 r 0 0 0 0 0 0 0 0 page 45 timer0 data register tdr0 w 1 1 1 1 1 1 1 1 page 45 timer0 input capture register cdr0 r 0 0 0 0 0 0 0 0 page 45 00e2 timer1 mode register tm1 r/w 00000000 page45 table 8-1 control registers
gms81c7008/7016 26 apr., 2001 ver 2.01 00e3 timer1 data register tdr1 w 1 1 1 1 1 1 1 1 page 45 pwm0 pulse period register t1ppr w 1 1 1 1 1 1 1 1 page 54 00e4 timer1 counter register t1 r 0 0 0 0 0 0 0 0 page 45 timer1 input capture register cdr1 r 0 0 0 0 0 0 0 0 page 45 timer1 pulse duty register t1pdr r/w 0 0 0 0 0 0 0 0 page 54 00e5 pwm0 high register pwm0hr w - - - - 0 0 0 0 page 54 00e6 timer2 mode register tm2 r/w - - 0 0 0 0 0 0 page 46 00e7 timer2 counter register t2 r 0 0 0 0 0 0 0 0 page 46 timer2 data register tdr2 w 1 1 1 1 1 1 1 1 page 46 timer2 input capture register cdr2 r 0 0 0 0 0 0 0 0 page 46 00e8 timer3 mode register tm3 r/w 00000000 page46 00e9 timer3 data register tdr3 w 1 1 1 1 1 1 1 1 page 46 pwm1 pulse period register t3ppr w 1 1 1 1 1 1 1 1 page 54 00ea timer3 counter register t3 r 0 0 0 0 0 0 0 0 page 46 timer3 input capture register cdr3 r 0 0 0 0 0 0 0 0 page 46 timer3 pulse duty register t3pdr r/w 0 0 0 0 0 0 0 0 page 46 00eb pwm1 high register pwm1hr w - - - - 0 0 0 0 page 54 00ec a/d converter mode register adcm r/w - 0 0 0 0 0 0 1 page 58 00ed a/d converter data register adr r undefined page 58 00ef watch timer mode register wtmr r/w - 0 - - 0 0 0 0 page 79 00f0 key scan port mode register ksmr r/w - - - - - - 0 0 page 69 00f1 lcd control register lcr r/w 0 0 0 0 0 0 0 0 page 71 00f2 lcd port mode register high lpmr r/w - - 0 0 0 0 0 0 page 71 00f3 ram paging register rpr r/w - - - - - - 0 0 page 24, page 71 00f4 basic interval timer register bitr r 0 0 0 0 0 0 0 0 page 43 clock control register ckctlr w - - - 0 0 1 1 1 page 43 00f5 system clock mode register scmr r/w 0 0 0 0 0 0 0 0 page 38 00fb lvd register lvdr r/w 0 0 0 0 0 - - - page 87 00fd buzzer data register bur w 0 0 0 0 0 0 0 0 page 62 00fe serial i/o mode register siom r/w 0 0 0 0 0 0 0 1 page 59 00ff serial i/o data register sior r/w undefined page 59 address register name symbol r/w initial value page 76543210 table 8-1 control registers registers are controlled by byte manipulation instruction such as ldm etc., do not use bit manipulation w registers are controlled by both bit and byte manipulation instruction. r/w instruction such as set1, clr1 etc. if bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. - : this bit location is reserved.
gms81c7008/7016 apr., 2001 ver 2.01 27 three registers are mapped on same address. two registers are mapped on same address. address timer/counter mode capture mode pwm mode e1 h t0 [r], tdr0 [w] cdr0 [r], tdr0 [w] - e3 h tdr1 [w] tdr1 [w] t1ppr [w] e4 h t1 [r] cdr1 [r] t1pdr [r/w] e7 h t2 [r], tdr2 [w] cdr2 [r], tdr2 [w] - e9 h tdr3 [w] tdr3 [w] t3ppr [w] ea h t3 [r] cdr3 [r] t3pdr [r/w] address basic interval timer f4 h bitr [r], ckctlr [w]
gms81c7008/7016 28 apr., 2001 ver 2.01 8.5 addressing mode the gms800 series mcu uses six addressing modes; ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing (1) register addressing register addressing accesses the a, x, y, c and psw. (2) immediate addressing ? ? ? ? #imm in this mode, second byte (operand) is accessed as a data imme- diately. example: 0435 adc #35h when g-flag is 1, then ram address is defined by 16-bit address which is composed of 8-bit ram paging register (rpr) and 8-bit immediate data. example: g=1, rpr=01 e45535 ldm 35h,#55h (3) direct page addressing ? ? ? ? dp in this mode, a address is specified within direct page. example; g=0 c535 lda 35h ;a ? ram[35h] 35 a+35h+c ? a 04 memory e4 0f100h data ? 55h ~ ~ ~ ~ data 0135h 35 0f102h 55 0f101h ? data 35 35h 0e551h data ? a ? ~ ~ ~ ~ c5 0e550h
gms81c7008/7016 apr., 2001 ver 2.01 29 (4) absolute addressing ? ? ? ? !abs absolute addressing sets corresponding memory data to data, i.e. second byte (operand i) of command becomes lower level ad- dress and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; 0735f0 adc !0f035h ;a ? rom[0f035h] the operation within data memory (ram) asl, bit, dec, inc, lsr, rol, ror example; addressing accesses the address 0135 h regardless of g-flag. 983501 inc !0135h ;a ? rom[135h] (5) indexed addressing x indexed direct page (no offset) ? ? ? ? {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h , g=1 d4 lda {x} ;acc ? ram[x] x indexed direct page, auto increment ? ? ? ? {x}+ in this mode, a address is specified within direct page by the x register and the content of x is increased by 1. lda, sta example; g=0, x=35 h db lda {x}+ x indexed direct page (8 bit offset) ? ? ? ? dp+x this address value is the second byte (operand) of command plus the data of -register. and it assigns the memory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, inc, lsr, rol, ror example; g=0, x=0f5 h 07 0f100h ~ ~ ~ ~ data 0f035h f0 0f102h 35 0f101h ? a+data+c ? a address: 0f035 98 0f100h ~ ~ ~ ~ data 135h 01 0f102h 35 0f101h ? data+1 ? data address: 0135 data d4 115h 0e550h data ? a ? ~ ~ ~ ~ data db 35h data ? a ? ~ ~ ~ ~ 36h ? x
gms81c7008/7016 30 apr., 2001 ver 2.01 c645 lda 45h+x y indexed direct page (8 bit offset) ? ? ? ? dp+y this address value is the second byte (operand) of command plus the data of y-register, which assigns memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute ? ? ? ? !abs+y sets the value of 16-bit absolute address plus y-register data as memory.this addressing mode can specify memory in whole ar- ea. example; y=55 h d500fa lda !0fa00h+y (6) indirect addressing direct page indirect ? ? ? ? [dp] assigns data address to use for accomplishing command which sets memory data (or pair memory) by operand. also index can be used with index register x,y. jmp, call example; g=0 3f35 jmp [35h] x indexed indirect ? ? ? ? [dp+x] processes memory data as data, assigned by 16-bit pair memory which is determined by pair data [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, x=10 h 1625 adc [25h+x] y indexed indirect ? ? ? ? [dp]+y processes memory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in direct page plus y- register data. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, y=10 h data 45 3ah 0e551h data ? a ? ~ ~ ~ ~ c6 0e550h 45h+0f5h=13ah d5 0f100h data ? a ~ ~ ~ ~ data 0fa55h 0fa00h+55h=0fa55h fa 0f102h 00 0f101h ? 0a 35h jump to ~ ~ ~ ~ 35 0fa00h e3 36h ? 3f 0e30ah next ~ ~ ~ ~ address 0e30ah 05 35h 0e005h ~ ~ ~ ~ 25 0fa00h e0 36h 16 0e005h data ~ ~ ~ ~ a + data + c ? a 25 + x(10) = 35h ?
gms81c7008/7016 apr., 2001 ver 2.01 31 1725 adc [25h]+y absolute indirect ? ? ? ? [!abs] the program jumps to address specified by 16-bit absolute ad- dress. jmp example; g=0 1f25e0 jmp [!0e025h] 05 25h 0e005h + y(10) ~ ~ ~ ~ 25 0fa00h e0 26h ? 17 0e015h data ~ ~ ~ ~ = 0e015h a + data + c ? a 25 0e025h jump to ~ ~ ~ ~ e0 0fa00h e7 0e026h ? 25 0e725h next ~ ~ ~ ~ 1f program memory address 0e30ah
gms81c7008/7016 32 apr., 2001 ver 2.01 9. i/o ports the gms81c7008/16 has seven ports (r0, r1, r2, r3, r4, r5 and r6), and lcd segment port seg0~seg23, and lcd com- mon port com0~com3, which are multiplexed with seg24~seg26. these ports pins may be multiplexed with an alternate function for the peripheral features on the device. in general, in a initial re- set state, r0,r1,r2, r3 ports are used as a general purpose input port and r4, r5, r6 and r7 ports are used as lcd segment drive output port. 9.1 registers for port port data registers the port data registers in i/o buffer in each seven ports (r0,r1,r2,r3,r4,r5,r6) are represented as a type d flip-flop, which will clock in a value from the internal bus in response to a "write to data register" signal from the cpu. the q output of the flip-flop is placed on the internal bus in response to a "read data register" signal from the cpu. the level of the port pin itself is placed on the internal bus in response to "read data register" sig- nal from the cpu. some instructions that read a port activating the "read register" signal, and others activating the "read pin" sig- nal port direction registers all pins have data direction registers which can define these ports as output or input. a "1" in the port direction register configure the corresponding port pin as output. conversely, write "0" to the corresponding bit to specify it as input pin. for example, to use the even numbered bit of r0 as output ports and the odd num- bered bits as input ports, write 55 h to address 0c8 h (r0 port direction register) during initial setting as shown in figure 9-1. figure 9-1 example of port i/o assignment all the port direction registers in the mcu have 0 written to them by reset function. on the other hand, its initial status is input. pull-up control registers the r0, r1, r2 and r3 ports have internal pull-up resistors. figure 9-2 shows a functional diagram of a typical pull-up port. it is connected or disconnected by pull-up control register (pur n ). the value of that resistor is typically 180k w . when a port is used as input, input logic is firmly either low or high, therefore external pull-down or pull-up resisters are re- quired practically. the gms81c7008/16 has internal pull-up, it can be logic high by pull-up that can be able to configure either connect or disconnect individually by pull-up control registers r0pu, r1pu, r2pu and r3pu. when ports are configured as inputs and pull-up resistor is select- ed by software, they are pulled to high. figure 9-2 pull-up port structure open drain port registers the r0, r1, r2 and r3 ports have open drain port resistors r0cr~r3cr. figure 9-3 shows a open drain port configuration by control reg- ister. it is selected as either push-pull port or open-drain port by r0cr, r1cr, r2cr and r3cr. figure 9-3 open-drain port structure i : input port write 55 h to port r0 direction register 0 1 0 1 0 1 0 1 i o i o i o i o r0 data r0 direction r1 data r1 direction 0c0h 0c1h 0c8h 0c9h 76543210 bit 76543210 port o : output port ~ ~ ~ ~ pull-up resistor port pin 1: connect 0: disconnect pull-up control bit vdd gnd vdd typ. 160k w port pin 1: open drain 0: push-pull open drain port selection bit gnd
gms81c7008/7016 apr., 2001 ver 2.01 33 9.2 i/o ports configuration r0 and r0dd register: r0 is an 8-bit cmos bidirectional i/o port (address 0c0 h ). each i/o pin can independently used as an input or an output through the r0dd register (address 0c8 h ). each port also can be set individually as pull-up port through the r0pu (address 0d0 h ), and as open drain register through the r0cr (address 0d4 h ). in addition, port r0 is multiplexed with various special features. the control register through the pmr (address 0d9 h ) and the siom (address 0fe h ) control the selection of alternate function. after reset, this value is 0, port may be used as normal i/o port. to use alternate function such as external interrupt, event counter input, serial interface data input, serial interface data output or se- rial interface clock, write 1 in the corresponding bit of pmr (address 0d9 h ) and siom (address 0fe h ). regardless of the direction register r0dd, the control registers of pmr and siom are selected to use as alternate functions, port pin can be used as a corresponding alternate features . r1 and r1dd register: r1 is an 2-bit cmos bidirectional i/o port (address 0c1 h ). each i/o pin can independently used as an input or an output through the r1dd register (address 0c9 h ). each port also can be set individually as pull-up port through the r1pu (address 0d1 h ), and as open drain register through the r1cr (address 0d5 h ). port pin alternate function r00 r01 r02 r03 r04 r05 r06 r07 int0 (external interrupt 0) int1 (external interrupt 1) int2 (external interrupt 2) ec0 (event counter input 0) ec2 (event counter input 2) sck (serial clock) so (serial data output) si (serial data input) r0 data register r0 address: 0c0 h reset value: 00 h r07 r06 r05 r04 r03 r02 r01 r00 port direction r0 direction register r0dd address: 0c8 h reset value: 00 h 0: input 1: output input / output data port mode register pmr address: 0d9 h reset value: 00 h 0: r00 1: int0 0 0: r01 1: int1 0: r02 1: int2 0: r03 1: ec0 0: r04 1: ec2 0: r30 1: buz 0: r31 1: pwm0/t1o 0: r32 1: pwm1/t3o 1 2 3 4 5 6 7 edge detection register ieds address: 0d8 h reset value: 00 h 0 1 2 3 4 5 - - int0 int1 int2 external interrupt edge select 00: reserved 01: falling (1-to-0 transition) 10: rising (0-to-1 transition) 11: both (rising & falling) r1 data register r1 address: 0c1 h reset value: 00 h r01 r00 port direction r1 direction register r1dd address: 0c9 h reset value: 00 h 0: input 1: output input / output data - - - --- - - -- --
gms81c7008/7016 34 apr., 2001 ver 2.01 r2 and r2dd register: r2 is an 8-bit cmos bidirectional i/o port (address 0c2 h ). each i/o pin can independently used as an input or an output through the r2dd register (address 0ca h ). each port also can be set individually as pull-up port through the r2pu (address 0d2 h ), and as open drain register through the r2cr (address 0d6 h ). in addition, port r2 is multiplexed with analog input port. port pin alternate function r20 r21 r22 r23 r24 r25 r26 r27 an0 (analog input 0) an1 (analog input 1) an2 (analog input 2) an3 (analog input 3) an4 (analog input 4) an5 (analog input 5) an6 (analog input 6) an7 (analog input 7) port pull-up r1 pull-up register r1pu address: 0d1 h reset value: 00 h 0: pull-up resistor off 1: pull-up resistor on port open drain r1 open drain control register r1cr address: 0d5 h reset value: 00 h 0: push pull 1: open drain - - ---- - - ---- r2 data register r2 address: 0c2 h reset value: 00 h r07 r06 r05 r04 r03 r02 r01 r00 port direction r2 direction register r2dd address: 0ca h reset value: 00 h 0: input 1: output input / output data port pull-up r2 pull-up register r2pu address: 0d2 h reset value: 00 h 0: pull-up resistor off 1: pull-up resistor on port open drain r2 open drain control register r2cr address: 0d6 h reset value: 00 h 0: push pull 1: open drain
gms81c7008/7016 apr., 2001 ver 2.01 35 r3 and r3dd register: r3 is an 8-bit cmos bidirectional i/o port (address 0c3 h ). each i/o pin can independently used as an input or an output through the r3dd register (address 0cb h ). each port also can be set individually as pull-up port through the r3pu (address 0d3 h ), and as open drain register through the r3cr (address 0d7 h ). in addition, port r3 is multiplexed with various special features. port pin alternate function r30 r31 r32 r33 r34 r35 r36 buz (buzzer driving output) pwm0 / t1o (pwm 0 output / timer 1 output) pwm1 /t3o (pwm 1 output / timer 3 output) - wdto (watchdog timer output) sx out (sub clock output) sx in (sub clock input) r3 data register r3 address: 0c3 h reset value: 00 h port direction r3 direction register r3dd address: 0cb h reset value: 00 h 0: input 1: output input / output data port pull-up r3 pull-up register r3pu address: 0d3 h reset value: 00 h 0: pull-up resistor off 1: pull-up resistor on port open drain r3 open drain control register r3cr address: 0d7 h reset value: 00 h 0: push pull 1: open drain - - - - r06 r05 r04 r03 r02 r01 r00 port selection register pmr address: 0d9 h reset value: 00 h 0: r00 1: int0 0 0: r01 1: int1 0: r02 1: int2 0: r03 1: ec0 0: r04 1: ec2 0: r30 1: buz 0: r31 1: pwm0/t1o 0: r32 1: pwm1/t3o 1 2 3 4 5 6 7 watch dog timer register wdtr address: 0df h reset value: --01_0010 b wdclr wdom wdck0 wdck1 wden wdoe - - lcd control register lcr address: 0f1 h reset value: 00 h lck0 lck1 dty0 dty1 brc lcden btc subm 0: r34 1: wdto 0: sx out , sx in (sub clock oscillation) 1: r35, r36(sub clock disable)
gms81c7008/7016 36 apr., 2001 ver 2.01 r4 and r4dd register: r4 is an 8-bit cmos bidirectional i/o port (address 0c4 h ). each i/o pin can independently used as an input or an output through the r4dd register (address 0cc h ). after reset, r4 port is used as lcd segment output seg0~seg7. to use general i/o ports user should be written ap- propriate value into the lpmr (0f3 h ). r5 and r5dd register: r5 is an 8-bit cmos bidirectional i/o port (address 0c5 h ). each i/o pin can independently used as an input or an output through the r4dd register (address 0cd h ). after reset, r5 port is used as lcd segment output seg8~seg15. to use general i/o ports user should be written appropriate value into the lpmr (0f3 h ). r6 and r6dd register: r6 is an 8-bit cmos bidirectional i/o port (address 0c6 h ). each i/o pin can independently used as an input or an output through the r6dd register (address 0ce h ). after reset, r6 port is used as lcd segment output seg16~seg23. to use general i/o ports user should be written appropriate value into the lpmr (0f3 h ). lcd pin function port pin seg0 (lcd segment 0 signal output) seg1 (lcd segment 1 signal output) seg2 (lcd segment 2 signal output) seg3 (lcd segment 3 signal output) seg4 (lcd segment 4 signal output) seg5 (lcd segment 5 signal output) seg6 (lcd segment 6 signal output) seg7 (lcd segment 7 signal output) r40 r41 r42 r43 r44 r45 r46 r47 lcd pin function port pin seg8 (lcd segment 8 signal output) seg9 (lcd segment 9 signal output) seg10 (lcd segment 10 signal output) seg11 (lcd segment 11 signal output) seg12 (lcd segment 12 signal output) seg13 (lcd segment 13 signal output) seg14 (lcd segment 14 signal output) seg15 (lcd segment 15 signal output) r50 r51 r52 r53 r54 r55 r56 r57 r4 data register r4 address: 0c4 h reset value: 00 h r47 r46 r45 r44 r43 r42 r41 r40 port direction r4 direction register r4dd address: 0cc h reset value: 00 h 0: input 1: output input / output data lcd pin function port pin seg16 (lcd segment 16 signal output) seg17 (lcd segment 17 signal output) seg18 (lcd segment 18 signal output) seg19 (lcd segment 19 signal output) seg20 (lcd segment 20 signal output) seg21 (lcd segment 21 signal output) seg22 (lcd segment 22 signal output) seg23 (lcd segment 23 signal output) r60 r61 r62 r63 r64 r66 r66 r67 r5 data register r5 address: 0c5 h reset value: 00 h r57 r56 r55 r54 r53 r52 r51 r50 port direction r5 direction register r5dd address: 0cd h reset value: 00 h 0: input 1: output input / output data r6 data register r6 address: 0c6 h reset value: 00 h r67 r66 r65 r64 r63 r62 r61 r60 port direction r6 direction register r6dd address: 0ce h reset value: 00 h 0: input 1: output input / output data
gms81c7008/7016 apr., 2001 ver 2.01 37 10. clock generator as shown in figure 10-1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the cpu and the peripheral hardware. it contains two oscillators: a main-frequency clock oscillator and a sub-frequency clock oscil- lator. power consumption can be reduced by switching them to the low power operation frequency clock can be easily obtained by attaching a resonator between the x in and x out pin and the sx in and sx out pin, respectively. the system clock can also be obtained from the external oscillator. the clock generator produces the system clocks forming clock pulse, which are supplied to the cpu and the peripheral hard- ware. the internal system clock can be selected by bit2, and bit3 of the system clock mode register(scmr). the register is shown in figure 10-2. to the peripheral block, the clock among the not-divided original clocks, divided by 2 , 4,..., up to 1024 can be provided. peripheral clock is enabled or disabled by stop instruction. figure 10-1 block diagram of clock generator cpu clock instruction cycle time x in = 4mhz sx in = 32.768khz ? 2 0.5 us 61 us ? 8 2.0 us 244 us ? 16 4.0 us 488 us ? 64 16.0 us 1953 us internal system clock (cpu clock) sx in pin prescaler 0 1 x in pin ? 1 peripheral clock mux ? 2 ? 4 ? 8 ? 16 ? 128 ? 256 ? 512 ? 1024 ? 32 ? 64 ? 2 ? 8 ? 16 ? 64 select clock scs[1:0] osc stop sycc<1> sycc<0> stop mode sleep mode ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 clock pulse f ex (mhz) ps0 ps3 ps2 ps4 ps1 ps10 ps9 ps5 ps6 ps7 4 frequency period 4m 1m 500k 250k 2m 125k 62.5k 250n 500n 1u 2u 4u 8u 16u 32u 64u 256u 128u 3.906k 7.183k 15.63k 31.25k ps8 f ex lcr<7> osc stop generator
gms81c7008/7016 38 apr., 2001 ver 2.01 the system clock is decided by bit1 (sycc1) of the system clock mode register(scmr). in selection sub clock, to oscillate or stop the main clock is decided by bit0 (sycc0) of scmr. on the ini- tial reset, internal system clock is ps1 which is the fastest and other clock can be provided by bit2 and bit3 of scmr. figure 10-2 scmr: system clock control registers system (cpu) clock control 00: main clock on 01: main clock on 10: sub clock on (main clock on) 11: sub clock on (main clock off) system clock source select 00: x in ? 2 01: x in ? 8 initial value: 00 h address: 0f5 h scmr 10: x in ? 16 11: x in ? 64 or sx in ? 2 or sx in ? 8 or sx in ? 16 or sx in ? 64 btcl 76543210 - - sycc1 sycc0 r/w r/w r/w r/w scs1 scs0 --
gms81c7008/7016 apr., 2001 ver 2.01 39 11. operation mode the system clock controller starts or stops the main-frequency clock oscillator and switches between the sub frequency clock. the operating mode is generally divided into the main-clock mode and the sub-clock mode, which are controlled by system clock mode register (scmr). figure 11-1shows the operating mode transition diagram. system clock control is performed by the system clock mode reg- ister, scmr. during reset, this register is initialized to 0 so that the main-clock operating mode is selected. main-clock operating mode this mode is fast-frequency operating mode. the cpu and the peripheral hardwares are operated on the high- frequency clock. at reset release, this mode is invoked. sub-clock operating mode this mode is low-frequency operating mode in this mode, the high-frequency clock oscillation is stops and low-frequency clock oscillation is active to operate the cpu and the peripheral hardware on the low-frequency clock, thereby re- ducing power consumption sleep mode in this mode, the cpu clock stops while peripherals and the os- cillation source continue to operate normally. stop mode in this mode, the system operations are all stopped, holding the internal states valid immediately before the stop at the low power consumption level. figure 11-1 operating mode main-clock mode stop mode reset operation r e s e t r e s e t main: according to scmr sub: oscillating main: stopped sub: oscillating main: oscillating sub: oscillating sleep mode release reset s t o p i n s t r u c t i o n r e f e r t o n o t e 1 i n s t r u c t i o n r e f e r t o n o t e 2 main sub - oscillating - oscillating main sub - oscillating - according to scmr sub-clock mode instruction instruction note1: reset key scan int. watch timer int. timer interrupt (ec0, ec2) external int. note2: reset all int. cpu stops, peripherals are operate. cpu and peripherals are stops, sio int. watchdog timer int.
gms81c7008/7016 40 apr., 2001 ver 2.01 11.1 operation mode switching in the main-clock operation mode, only the high-frequency clock oscillator is used. in the sub-clock operation mode, the high-frequency clock oscil- lation stops, enabling the low power voltage operation or the low power consumption operation. instruction execution does not stop when the operation speed switching is performed. however, some peripheral hardware capabilities may be affected. for de- tails, refer to the description of the relevant operation. the following describes the switching between the main-clock and the sub-clock operations. during reset, the system clock mode register is initialized at the main-clock mode. it must be set to the sub-clock operation for the low-power consumption mode. switching from main clock operation to sub- clock operation first, write 10 b into lower 2 bits of scmr to switch the main system clock to the sub-frequency clock. next, write 11 b to turn off main frequency oscillation. example: : : mov scmr,#0000_xx10b ; switch to sub mode mov scmr,#0000_xx11b ; turn off main clock : : returning from sub clock operation to main clock operation first, write 10 b into lower 2 bits of the scmr to turn on the main-frequency oscillation, when the stabilization (warm-up) has been taken by the software delay routine. sub clock operation mode can also be released by setting the reset pin to low, which immediately performs the reset operation. after reset, the gms81c7008/16 is placed in main frequency operation mode. example: : : : mov scmr,#0000_xx10b ; turn on main-clock call delay ; wait until stable mov scmr,#0000_xx00b ; move to main mode : : : ;20ms software delay at fxin=4mhz delay: ldy #0 dlp0: lda #0 dlp1: nop inc a bcc dlp1 inc y cmpy #20 bcc dlp0 ret shifting from the normal operation to the sleep mode by setting bit 0 of smr, the cpu clock stops and the sleep mode is invoked. the cpu stops while other peripherals are op- erate normally. the way of release from this mode is reset and all available in- terrupts. for more detail, see "20.1 sleep mode" on page 81 shifting from the normal operation to the stop mode by executing stop instruction, the main-frequency clock oscil- lation stops and the stop mode is invoked. but sub-frequency clock oscillation is operated continuously. after the stop operation is released by reset, the operation mode is changed to main-clock mode. the methods of release are reset, key scan interrupt, watch timer interrupt, timer/event counter1 (ec0, ec2 pin), and ex- ternal interrupt. for more details, see "20.2 stop mode" on page 82. note: in the stop and sub clock operating modes, the power consumed by the oscillator and the internal hard- ware is reduced. however, the power for the pin interface (depending on external circuitry and program) is not directly associated with the low-power consumption operation. this must be considered in system design as well as interface circuit design.
gms81c7008/7016 apr., 2001 ver 2.01 41 figure 11-2 system clock switching timing operation clock ~ ~ ~ ~ sub-clock operation main-clock operation sub freq. clock main freq. clock (x in pin) (sx in pin) changed to the sub-clock scmr ? xxxx xx10 b ~ ~ ~ ~ ~ ~ operation clock ~ ~ main-clock operation stabilizing time > 20ms sub freq. clock main freq. clock (x in pin) (sx in pin) changed to the transition changed to the main-clock scmr ? xxxx xx10 b scmr ? xxxx xx00 b ~ ~ ~ ~ sub-clock operation ~ ~ (a) main clock mode ? ? ? ? sub clock mode (b) sub clock ? ? ? ? main clock or 01 b turn off main clock scmr ? xxxx xx11 b
gms81c7008/7016 42 apr., 2001 ver 2.01 12. basic interval timer the gms81c7008/16 has one 8-bit basic interval timer that is free-run and can not stop. block diagram is shown in figure 12-1. in addition, the basic interval timer generates the time base for watchdog timer counting. it also provides a basic interval timer interrupt (bitif). as the count overflow from ff h to 00 h , this overflow causes the interrupt to be generated. the basic interval timer is controlled by the clock control register (ckctlr) shown in figure 12-2. source clock can be selected by lower 3 bits of ckctlr. the registers bitr and ckctlr are located at same address, and address 0f9 h is read as a bitr, and written to ckctlr. figure 12-1 block diagram of basic interval timer table 12-1 basic interval timer interrupt time mux basic interval timer interrupt select input clock 3 basic interval timer source clock 8-bit up-counter bts[2:0] btcl ? 8 ? 1024 ? 512 ? 256 ? 128 ? 64 ? 32 ? 16 to watchdog timer (wdtck) ckctlr clear overflow internal bus line clock control register [0f4 h ] [0f9 h ] bitif read prescaler bitr f xin f sxin 0x 1x scmr[1:0] bts[2:0] cpu source clock interrupt (overflow) period (ms) @ f xin = 4mhz @ f sxin = 32.768khz 000 001 010 011 100 101 110 111 ? 8 ? 16 ? 32 ? 64 ? 128 ? 256 ? 512 ? 1024 0.512 1.024 2.048 4.096 8.192 16.384 32.768 65.536 62.5ms 125ms 250ms 500ms 1000ms 2000ms 4000ms 8000ms
gms81c7008/7016 apr., 2001 ver 2.01 43 figure 12-2 bitr: basic interval timer mode register example 1 : interrupt request flag is generated every 8.192ms at 4mhz. : ldm ckctlr,#0ch set1 bite ei : btcl 76543210 - - bts1 basic interval timer source clock select 000: f xin ? 8 001: f xin ? 16 010: f xin ? 32 011: f xin ? 64 100: f xin ? 128 101: f xin ? 256 110: f xin ? 512 111: f xin ? 1024 clear bit 0: normal operation, free-run 1: clear 8-bit counter (bitr) to 0 and count up again. initial value: ---0 0111 b address: 0f4 h ckctlr initial value: undefined address: 0f4 h bitr both register are in same address, when write, to be a ckctlr, when read, to be a bitr. caution: 8-bit free-run binary counter bts0 bts2 btcl btcl 76543210 or f sxin ? 8 or f sxin ? 16 or f sxin ? 32 or f sxin ? 64 or f sxin ? 128 or f sxin ? 256 or f sxin ? 512 or f sxin ? 1024 r ww ww w rr r rr r r bck - this bit becomes to 0 automatically after one machine cycle. for the test purpose. this bit must be cleared to 0 for normal operation, otherwise bit clock source is form sub-clock.
gms81c7008/7016 44 apr., 2001 ver 2.01 13. timer/event counter the gms81c7008/16 has four timer/event counters. each mod- ule can generate an interrupt to indicate that an event has occurred (i.e. timer match). timer 0 and timer 1 are can be used either two 8-bit timer/ counter or one 16-bit timer/counter with combine them. also timer 2 and timer 3 can be joined as a 16-bit timer/counter. in the timer function, the register is increased every internal clock input. thus, one can think of it as counting internal clock input. the count rate is 1/2 to 1/2048 of the oscillator frequency. in the counter function, the register is incremented in response to a 0-to-1 (rising edge) transition at its corresponding external input pin, ec0 or ec2 pin. in addition the capture function, the register is incremented in response external or internal clock sources same with timer or counter function. when external clock edge input, the count reg- ister is captured into capture data register correspondingly. it has five operating modes: 8-bit timer/counter, 16-bit timer/ counter, 8-bit capture, 16-bit capture, pwm mode which are selected by bit in timer mode register tm n . in operation of timer 2, timer 3, their operations are same with timer 0, timer 1, respectively. when programming the software, you may refer to following ex- ample . example 1: timer 0 = 8-bit timer mode, 8ms interval at 4mhz timer 1 = 8-bit timer mode, 4ms interval at 4mhz timer 2 = 16-bit event counter mode ldm scmr,#0 ;main clock mode ldm tdr0,#249 ldm tm0,#0001_0011b ldm tdr1,#124 ldm tm1,#0000_1111b ldm tdr2,#1fh ldm tdr3,#4ch ldm tm2,#0001_1111b ldm tm3,#0100_1100b set1 t0e set1 t2e ei : : example 2: timer0 = 16-bit timer mode, 0.5s at 4mhz timer2 = 2ms 8-bit timer mode at 4mhz timer3 = 250us 8-bit timer mode at 4mhz ldm scmr,#0 ;main clock mode ldm tdr0,#23h ldm tdr1,#0f4h ldm tm0,#0fh ;fxin/32, 8us ldm tm1,#4ch ldm tdr2,#249 ldm tdr3,#124 ldm tm2,#0fh ;fxun/32, 8us ldm tm3,#0dh ;fxin/8, 2us set1 t0e set1 t2e set1 t3e ei : : example 3: timer0 = 8-bit timer mode, 2ms interval at 4mhz timer1 = 8-bit capture mode, 2us sampling count. ldm tdr0,#249 ;250x8=2000us ldm tm0,#0fh ;fxin/32, 8us ldm ieds,#xxxx_01xxb ;falling ldm pmr,#xxxx_xx1xb ;as int1 ldm tdr1,#0ffh ldm tm1,#0001_1011b ;2us set1 t0e ;enable timer 0 set1 t1e ;enable timer 1 set1 int1e ;enable ext. int1 ei : : x: dont care. example 4: timer0 = 8-bit timer mode, 2ms interval at 4mhz timer2 = 16-bit capture mode, 8us sampling count. ldm tdr0,#249 ldm tm0,#0fh ldm ieds,#xx11_xxxxb ldm pmr4,#xxxx_x1xxb ldm tdr2,#0ffh ;max ldm tdr3,#0ffh ;max ldm tm2,#xx10_1111b ;/32 ldm tm3,#x10x_11xxb set1 t0e ;enable timer 0 set1 t2e ;enable timer 2 set1 int2e ;enable ext. int2 ei : : x: dont care.
gms81c7008/7016 apr., 2001 ver 2.01 45 figure 13-1 tm0, tm1, tdrn registers btcl 76543210 cap0 t0ck1 initial value: 00 h address: 0e0 h tm0 t0ck0 t0cn t0st 76543210 initial value: 0ff h address: 0e1 h , 0e3 h , 0e7 h , 0e9 h tdr0~tdr3 compare data registers wwwwwwww r/w r/w r/w r/w r/w r/w t0ck2 timer 0 mode register basic interval timer source clock select 000: f xin ? 2 001: f xin ? 4 010: f xin ? 8 011: f xin ? 32 100: f xin ? 128 101: f xin ? 512 110: f xin ? 2048 111: ec0 (external event input 0) 0: disable count 1: enable count 0: stop count 1: clearing the t0 counter and start count again timer/counter 0 enable flag timer/counter 0 start/stop control flag 0: timer mode 1: capture mode capture mode enable -- btcl 76543210 pwme0 t1ck1 initial value: 00 h address: 0e2 h tm1 t1ck0 t1cn t1st r/w r/w r/w r/w r/w r/w cap1 timer 1 mode register timer/counter 1 source clock select 00: f xin 01: f xin ? 2 10: f xin ? 8 11: timer 0 clock 0: disable count 1: enable count 0: stop count 1: clearing the t1 counter and start count again timer/counter 1 enable flag timer/counter 1 start/stop control flag 0: timer mode 1: capture mode capture mode enable pol0 16bit0 r/w r/w 0: disable 1: enable pwm enable bit 0: active low 1: active high pwm duty control 0: 8-bit mode 1: 16-bit mode mode selection or f sxin or f sxin ? 2 or f sxin ? 8 (depend on scmr) or f sxin ? 2 or f sxin ? 4 or f sxin ? 8 or f sxin ? 32 or f sxin ? 128 or f sxin ? 512 or f sxin ? 2048
gms81c7008/7016 46 apr., 2001 ver 2.01 figure 13-2 tm2, tm3 registers btcl 76543210 cap2 t2ck1 initial value: 00 h address: 0e6 h tm2 t2ck0 t2cn t2st r/w r/w r/w r/w r/w r/w t2ck2 timer 2 mode register timer/counter 2 source clock select 000: f xin ? 2 001: f xin ? 4 010: f xin ? 8 011: f xin ? 32 100: f xin ? 128 101: f xin ? 512 110: f xin ? 2048 111: ec2 (external event input 2) 0: disable count 1: enable count 0: stop count 1: clearing the t0 counter and start count again timer/counter 2 enable flag timer/counter 2 start/stop control flag 0: timer mode 1: capture mode capture mode enable -- btcl 76543210 pwme1 t3ck1 initial value: 00 h address: 0e8 h tm3 t3ck0 t3cn t3st r/w r/w r/w r/w r/w r/w cap3 timer 3 mode register timer/counter 3 source clock selection 0: disable count 1: enable count 0: stop count 1: clearing the t3 counter and start count again timer/counter 3 enable flag timer/counter 3 start/stop control flag 0: timer mode 1: capture mode capture mode enable pol1 16bit1 r/w r/w 0: disable 1: enable pwm enable bit 0: active low 1: active high pwm1 duty control 0: 8-bit mode 1: 16-bit mode mode selection 00: f xin 01: f xin ? 2 10: f xin ? 8 11: timer 2 clock or f sxin or f sxin ? 2 or f sxin ? 8 (depend on scmr) or f sxin ? 2 or f sxin ? 4 or f sxin ? 8 or f sxin ? 32 or f sxin ? 128 or f sxin ? 512 or f sxin ? 2048 76543210 initial value: 00 h address: 0e1 h , 0e4 h , 0e7 h , 0ea h t0~t3 count registers rrrrrrrr cdr0~cdr3
gms81c7008/7016 apr., 2001 ver 2.01 47 13.1 8-bit timer / counter mode the gms81c7008/16 has four 8-bit timer/counters, timer 0, timer 1, timer 2, timer 3 which are shown in figure 13-3, fig- ure 13-4. the timer or counter function is selected by control registers tmn. to use as an 8-bit timer/counter mode, cap0, cap1, 16bit0 and pwme bits should be cleared to 0. these timers have each 8-bit count register and data register. the count register is increased by every internal or external clock input. the internal clock has a prescaler divide ratio option of 2~2048 selected by control bits of register tm n (n=0,1,2,3). figure 13-3 8-bit timer/counter 0, 1 ec0 pin ? 2 ? 4 ? 8 mux prescaler t0if clear 0: stop 1: clear and start 000 001 010 timer 0 interrupt mux t1if clear 0: stop 1: clear and start timer 1 interrupt ? 8 ? 2 ? 1 tdr0 (8-bit) t1 (8-bit) tdr1 (8-bit) t0 (8-bit) comparator comparator timer 0 timer 1 r31/t1o/pwm0 f/f btcl 76543210 - cap0 t0ck1 initial value: 00 h address: 0e0 h tm0 t0ck0 t0cn t0st -t0ck2 xx x means dont care 0 pin ? 32 ? 128 ? 512 ? 2048 011 100 101 110 111 00 01 10 11 btcl pol0 pwme0 t1ck1 initial value: 00 h address: 0e2 h tm1 t1ck0 t1cn t1st 16bit0 cap1 x000 edge detector pmr.6 f xin f sxin 0x 1x scmr[1:0] xxxx xx x x x t0cn t0ck[2:0] 1 0 t0st t1st t1cn 1 0 t1ck[1:0] [0d9 h .6] [0e1 h ] [0e1 h ] [0e4 h ] [0e3 h ]
gms81c7008/7016 48 apr., 2001 ver 2.01 note: the contents of timer data register tdrx should be initialized with 1 h ~ff h , not to 0 h , because it is not to de- fined before reset. in the timer 0, timer register t0 increments from 00 h until it matches with tdr0 and then reset to 00 h . the match output of timer 0 generates timer 0 interrupt (latched in t0if bit) as tdrx and tx register are in same address, when reading it as a tx, written to tdrx. in counter function, the counter is increased every 0-to-1 (rising edge) transition of ec0 or ec2 pin. in order to use counter func- tion, the bit 3 and bit 4 of the port mode register pmr are set to 1 by software. the timer 0 can be used as a counter by pin ec0 input. similarly, timer 2 can be used by pin ec2 input. figure 13-4 8-bit timer/counter 2, 3 ec2 pin ? 2 ? 4 ? 8 mux prescaler t2if clear 0: stop 1: clear and start 000 001 010 timer 2 interrupt mux t3if clear 0: stop 1: clear and start timer 3 interrupt ? 8 ? 2 ? 1 tdr2 (8-bit) t3 (8-bit) tdr3 (8-bit) t2 (8-bit) comparator comparator timer 2 timer 3 r32/t3o/pwm0 f/f btcl 76543210 - cap2 t2ck1 initial value: 00 h address: 0e6 h tm2 t2ck0 t2cn t2st -t2ck2 xx x means dont care 0 pin ? 32 ? 128 ? 512 ? 2048 011 100 101 110 111 00 01 10 11 btcl pol1 pwme1 t3ck1 initial value: 00 h address: 0e8 h tm3 t3ck0 t3cn t3st 16bit1 cap3 x000 edge detector pmr.7 f xin f sxin 0x 1x scmr[1:0] xxxx xx x x x t2cn t2ck[2:0] 1 0 t2st t3st t3cn 1 0 t3ck[1:0] [0d9 h .7] [0e7 h ] [0e7 h ] [0ea h ] [0e9 h ]
gms81c7008/7016 apr., 2001 ver 2.01 49 8-bit timer mode in the timer mode, the internal clock is used for counting up. thus, you can think of it as counting internal clock input. the contents of tdr n (n=0,1,2,3) are compared with the contents of up-counter, t n (n=0,1,2,3). if match is found, a timer 1 interrupt (t1if) is generated and the up-counter is cleared to 0. counting up is resumed after the up-counter is cleared. as the value of tdr n can be re-written by software, time interval is set as you want figure 13-5 timer mode timing chart figure 13-6 timer count example 0 n-2 2 0 n 3 n-1 n source clock up-counter tdr1 t1if interrupt start count 1 23 1 4 match detect counter clear ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt occur interrupt interrupt period up-count ~ ~ ~ ~ 0 1 2 3 4 5 6 7a 7d 7c count pulse = 8 m s x 125 7b match example: make 1ms interrupt using by timer0 at 4mhz ldm tm0,#0fh ; divide by 32 ldm tdr0,#124 ; 8us x (124+1)= 1ms set1 t0e ; enable timer 0 interrupt ei ; enable master interrupt period when tdr0 = 124 d = 7c h f xin = 4 mhz interrupt period = 4 10 6 hz 1 32 (124+1) = 1 ms tm0 = 0000_1111 b (8-bit timer mode, prescaler divide ratio ? ? 32) 8 m s (tdr0 = t0) 7d 0
gms81c7008/7016 50 apr., 2001 ver 2.01 8-bit event counter mode in this mode, counting up is started by an external trigger. this trigger means rising edge of the ec0 or ec2 pin input. source clock is used as an internal clock selected with timer mode regis- ter tm0, tm1, tm2 or tm3. the contents of timer data register tdr n (n = 0,1,2,3,........,ff) are compared with the contents of the up-counter t n . if a match is found, an timer interrupt request flag t n if is generated, and the counter is cleared to 0. the counter is restart and count up continuously by every rising edge of the ec n pin input. the maximum frequency applied to the ec n pin is f xin /2 [hz]. in order to use event counter function, the bit 3, 4 of the port mode register pmr (address 0d9 h ) is required to be set to 1. after reset, the value of timer data register tdr n is undefined, it should be initialized to between 1 h ~ff h not to "0". the interval period of timer is calculated as below equation. figure 13-7 event counter mode timing chart figure 13-8 count operation of timer / event counter period (sec) 1 f xin --------- - 2 divide ratio tdrn = 0 1 2 1 0 n 2 ~ ~ ~ ~ ~ ~ n-1 n ~ ~ ~ ~ ~ ~ ec n pin input up-counter tdr1 t1if interrupt start count timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt stop clear & start disable enable start & stop t1st t1cn control count up-count ~ ~ ~ ~ t1st = 0 t1st = 1 t1cn = 0 t1cn = 1
gms81c7008/7016 apr., 2001 ver 2.01 51 13.2 16-bit timer / counter mode the timer register is being run with all 16 bits. a 16-bit timer/ counter register t0, t1 are incremented from 0000 h until it matches tdr0, tdr1 and then resets to 0000 h . the match out- put generates timer 0 interrupt. the clock source of the timer 0 is selected either internal or ex- ternal clock by bit t0sl1, t0sl0. even if the timer 0 (including the timer 1) is used as a 16-bit timer, the timer 2 and timer 3 can still be used as either two 8- bit timer or one 16-bit timer by setting the tm2. reversely, even if the timer 2 (including the timer 3) is used as a 16-bit timer, the timer 0 and timer 1 can still be used as 8-bit timer indepen- dently. figure 13-9 16-bit timer/counter t0if clear 0: stop 1: clear and start t0st t0ck[2:0] timer 0 interrupt t0cn comparator timer 0 + timer 1 ? timer 0 (16-bit) higher byte lower byte compare data t0 (16-bit) 1 0 (not timer 1 interrupt) 76543210 initial value: 00 h address: 0e0 h tm0 xx x x x x 0x x means dont care ? 2 ? 4 ? 8 mux prescaler 000 001 010 ? 32 ? 128 ? 512 ? 2048 011 100 101 110 111 edge detector ec0 pin tm1 btcl x1 00 1 1xx pol0 pwme0 t1ck1 initial value: 00 h address: 0e2 h t1ck0 t1cn t1st 16bit0 cap1 btcl - cap0 t0ck1 t0ck0 t0cn t0st -t0ck2 76543210 initial value: 00 h address: 0e6 h tm2 xx x x x x 0x tm3 btcl x1 00 1 1xx pol1 pwme1 t3ck1 initial value: 00 h address: 0e8 h t3ck0 t3cn t3st 16bit1 cap3 btcl - cap2 t2ck1 t2ck0 t2cn t2st -t2ck2 r31/t1o/pwm0 f/f pin pmr.6 t1 tdr0 tdr1 f xin f sxin 0x 1x scmr[1:0] t2if clear 0: stop 1: clear and start t2st t2ck[2:0] timer 2 interrupt t2cn comparator timer 0 + timer 1 ? timer 0 (16-bit) higher byte lower byte compare data t2 (16-bit) 1 0 (not timer 3 interrupt) ? 2 ? 4 ? 8 mux prescaler 000 001 010 ? 32 ? 128 ? 512 ? 2048 011 100 101 110 111 edge detector ec2 pin r32/t3o/pwm1 f/f pin pmr.7 t3 tdr2 tdr3 f xin f sxin 1x 1x scmr[1:0] [0d9 h .6] [0d9 h .7] x means dont care
gms81c7008/7016 52 apr., 2001 ver 2.01 13.3 8-bit capture mode the capture mode can be used to measure the pulse width be- tween two edges. the timer 0 capture mode is set by bit cap0 of timer mode register tm0, and the timer 1 capture mode is set by cap1 of timer mode register tm1 as shown in figure 13-10. timer 2 and timer 3 have same architecture with timer 0 and timer 1. the timer/counter register is incremented in response internal or external input. this counting function is same with normal timer mode, and timer interrupt is generate when timer register t0 (t1, t2, t3) increase and match tdr0 (tdr1, tdr2, tdr3). timer/counter still does the above, but with the added feature that a edge transition at external input int n pin causes the current . figure 13-10 8-bit capture mode (timer0/timer1 case) f timer f xin 2 prescaler value tdr 1 + () -------------------------------------------------------------------------------- = t0ck[2:0] ? 2 ? 4 ? 8 mux 000 001 010 ? 32 ? 128 ? 512 ? 2048 011 100 101 110 111 edge detector ec0 pin t0cn int0if 0: stop 1: clear and start int0 interrupt cdr0 (8-bit) t0 (8-bit) 01 10 11 capture ieds[1:0] cdr0 (8-bit) cdr0 t0if timer 0 interrupt comparator compare data cdr0 (8-bit) tdr0 (8-bit) int0 pin t0st clear clear t1ck[1:0] ? 1 ? 2 ? 8 mux 00 01 10 11 t1cn 0: stop 1: clear and start cdr0 (8-bit) t1 (8-bit) cdr0 (8-bit) cdr1 t1if timer 1 interrupt comparator compare data cdr0 (8-bit) tdr1 (8-bit) t1st clear int1if int1 interrupt 01 10 11 capture ieds[3:2] int1 pin clear 76543210 initial value: 00 h address: 0e0 h tm0 xx x x x x 1x tm1 btcl x0 01 xxxx pol0 pwme0 t1ck1 initial value: 00 h address: 0e2 h t1ck0 t1cn t1st 16bit0 cap1 btcl - cap0 t0ck1 t0ck0 t0cn t0st -t0ck2 ? 1 prescaler f xin f sxin 0x 1x scmr[1:0] r31/t1o/pwm0 f/f pin pmr.6 [0d9 h .6] f ex
gms81c7008/7016 apr., 2001 ver 2.01 53 value in the timer counter register (t0,t1), to be captured and stored into registers cdr n (cdr0, cdr1), respectively. after capture, the timer counter register is cleared and restarts by hard- ware. at this time, reading the address e1 h as a cdr0, not t0. t0, tdr0, cdr0 are located at same address. the other cdr1~cdr3 are same. refer to timer registers of page 27. it has three transition modes: falling edge, rising edge, both edge which are selected by interrupt edge selection register ieds. refer to 17.4 external interrupt on page 68. in addition, the transition at int n pin generate an interrupt. note: the cdrn and tn are in same address.in the cap- ture mode, reading operation is read as cdrn, not tn be- cause addressing path is opened to the cdrn. figure 13-11 16-bit capture mode 13.4 16-bit capture mode 16-bit capture mode is the same as 8-bit capture, except that the timer register is being run will 16 bits. configuration is shown in figure 13-11. 13.5 timer output port mode the gms81c7008/16 has a function of timer compare output. to pulse out, the timer match can goes out to port pin (t1o, t3o) as shown in figure 13-3, figure 13-4 and figure 13-9. thus pulse out is generated by the timer match. these operation is implemented to pin t1o, t3o. this pin output the signal hav- ing 50% duty square wave and output frequency is same as below equation. to use this function, the bit 6 and bit 7 of port mode register (pmr) are set or clear properly. in addition, 16-bit timer output mode is available, also t0ck[2:0] ? 2 ? 4 ? 8 mux 000 001 010 ? 32 ? 128 ? 512 ? 2048 011 100 101 110 111 edge detector ec0 pin t0cn int0if 0: stop 1: clear and start int0 interrupt 01 10 11 capture ieds[1:0] t0if timer 0 interrupt comparator compare data int0 pin t0st clear clear prescaler f xin f sxin 0x 1x scmr[1:0] r31/t1o/pwm0 f/f pin pmr.6 cdr1 cdr0 tdr1 tdr0 t1 t0 btcl 76543210 - cap0 t0ck1 initial value: 00 h address: 0e0 h tm0 t0ck0 t0cn t0st -t0ck2 xx x means dont care 1 btcl pol0 pwme0 t1ck1 initial value: 00 h address: 0e2 h tm1 t1ck0 t1cn t1st 16bit0 cap1 x 10 1 11xx xx x x x [0d9 h .6] 16 bits msb lsb f ex
gms81c7008/7016 54 apr., 2001 ver 2.01 13.6 pwm mode the gms81c70xx and gms81c71xx have two high speed pwm (pulse width modulation) functions which shared with timer 1 and timer 3. figure 13-12 pwm mode t1ck[1:0] mux ? 8 ? 2 ? 1 11 10 01 00 t1cn t1ppr (8-bit) s comparator clear t1st 76543210 tm1 btcl x0 10 xxxx pol0 pwme0 t1ck1 initial value: 00 h address: 0e2 h t1ck0 t1cn t1st 16bit0 cap1 prescaler f xin f sxin 0x 1x scmr[1:0] 2 bit t1 (8-bit) (note1) t1pdr (8-bit) 2 bit r q t1pdr (8-bit) 2 bit t0 clock source (from timer 0) pol0 r31/t1o/pwm0 pin pmr.6 pwm0hr ----xxxx - pwm02 initial value: 00 h address: 0e5 h pwm03 - pwm00 pwm01 -- duty high period high pwm[01:00] [0e4 h ] [0e5 h ] pwm[03:02] [0e3 h ] [0e5 h ] [0d9 h .6] 2 bit note1 : in the pwm mode, 2 bits are added by hardware automatically. t3ck[1:0] mux ? 8 ? 2 ? 1 11 10 01 00 t3cn t3ppr (8-bit) s comparator clear t3st 76543210 tm3 btcl x0 10 xxxx pol1 pwme1 t3ck1 initial value: 00 h address: 0e8 h t3ck0 t3cn t3st 16bit1 cap3 prescaler f xin f sxin 0x 1x scmr[1:0] 2 bit t3 (8-bit) (note1) t3pdr (8-bit) 2 bit r q t3pdr (8-bit) 2 bit t2 clock source (from timer 2) pol1 r32/t3o/pwm1 pin pmr.7 pwm1hr ----xxxx - pwm12 initial value: 00 h address: 0eb h pwm13 - pwm10 pwm11 -- duty high period high pwm[11:10] [0ea h ] [0eb h ] pwm[13:12] [0e9 h ] [0eb h ] [0d9 h .7] 2 bit f ex
gms81c7008/7016 apr., 2001 ver 2.01 55 note: whenever change the register content of period or duty of pwm output, the timer counter tn must be stopped and restart again by software. the pwm0 will be explained in this chapter. other pwm1 has same architecture. pin r32/t1o/pwm0 outputs up to a 10-bit resolution pwm output. this pin should be configure as a pwm output to set bit prm0.6 to 1. the period of the pwm output is determined by the t1ppr (pwm0 period register) and pwm0hr[3:2] and the duty is de- termined by the t1pdr (pwm0 duty register) and pwm0hr[1:0]. the user writes the lower 8-bit period value to the t1ppr and the higher 2-bit period value to the pwm0hr[3:2]. and writes duty value to the t1pdr and the pwm0hr[1:0] same way. the t1pdr is configure as a double buffering for glitchless pwm output. in, the duty data is transferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle) the relation between frequency and resolution is in inverse pro- portion. table 13-1 shows the pwm frequency in each clock source. if it needed higher frequency of pwm, it should be re- duced resolution. figure 13-13 example of register setting the bit pol0 of tm0 decides the polarity of duty cycle. if the duty value is set same to the period value, the pwm output is determined by the bit pol0 (1: high, 0: low). and if the duty value is set to 00 h , the pwm output is determined by the bit pol0 (1: low, 0: high). it can be changed duty value when the pwm output. however the changed duty value is output after the current period is over. and it can be maintained the duty value at present output when changed only period value shown as figure 13-14. as it were, the absolute duty time is not changed in varying frequency. but the changed period value must greater than the duty value. at pwm output start command, one first pulse would be output abnormally. because if user writes register values while timer is in operation, these register could be set with certain values at first. to prevent this operation, user must stop pwm timer clock and then set the duty and the period register values. t1 ~ ~ ~ ~ 01 h 02 h 03 h 04 h 256 h 257 h 258 h 3e7 h 01 h ~ ~ ~ ~ ~ ~ pwm output duty; (257 h +1) x 500ns = 300us 00 h 00 h ~ ~ ~ ~ 02 h clock source period; (3e7 h +1) x 500ns = 500us t1ppr pwm0hr 11 11100111 t1pdr 10 01010111 [0e4 h ] [0e3 h ] [0e5 h ] ----1110 period duty ~ ~
gms81c7008/7016 56 apr., 2001 ver 2.01 example: timer1 = 2khz, 30% duty pwm mode ldm tm1,#00h ldm t1ppr,#0e8h ldm t1pdr,#58h ldm pwm0hr,0000_1110b ldm tm1,#1010_1011b refer to figure 13-13. figure 13-14 example of changing the period in absolute duty cycle at 4mhz resolutio n pwm clock source f xin ? ? ? ? 1f xin ? ? ? ? 2f xin ? ? ? ? 1024 10-bit 3.9khz 1.95khz 3.8hz 9-bit 7.8khz 3.9khz 7.6hz 8-bit 15.6khz 7.8khz 15.3hz 7-bit 31.2khz 15.6khz 30.5hz table 13-1 pwm frequency vs. resolution at 4mhz source t1 pwm pol=1 duty cycle period cycle [ (d h +1) x 2us = 28us, 35.7khz ] pwmhr = 00 h t1ppr = 0d h t1pdr = 04 h t1ck[1:0] = 10 (2us) 00 01 02 03 04 05 07 08 0a 0b 0c 0d 00 01 02 03 04 05 06 07 08 09 00 01 02 03 06 09 04 [ (4+1) x 2us = 10us ] duty cycle [ (4+1) x 2us =10us ] period cycle [ (9+1) x 2us = 20us, 50khz ] duty cycle [ (4+1) x 2us = 10us ] write 09 h to t1ppr period changed clock
gms81c7008/7016 apr., 2001 ver 2.01 57 14. analog digital converter the analog-to-digital converter (a/d) allows conversion of an analog input signal to a corresponding 8-bit digital value. the a/ d module has eight analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which generates the result via successive ap- proximation. the analog supply voltage is connected to av dd of ladder resistance of a/d module. the a/d module has two registers which are the control register adcm and a/d result register adr. the register adcm, shown in figure 14-4, controls the operation of the a/d converter mod- ule. the port pins can be configured as analog inputs or digital i/ o. to use analog inputs, i/o is selected input mode by r2dd di- rection register. how to use a/d converter the processing of conversion is start when the start bit adst is set to 1. after one cycle, it is cleared by hardware. the register adr contains the results of the a/d conversion. when the con- version is completed, the result is loaded into the adr, the a/d conversion status bit adsf is set to 1, and the a/d interrupt flag aif is set. the block diagram of the a/d module is shown in figure 14-1. the a/d status bit adsf is set automatically when a/d conversion is completed, cleared when a/d conversion is in process. the conversion time takes maximum 20 us (at f xin =4 mhz). figure 14-1 a/d block diagram a/d converter cautions (1) input voltage range of an0 to an7 the input voltage of an0 to an7 should be within the specifica- tion range. in particular, if a voltage above av dd or below av ss is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. the conversion values of the other channels may also be affected. (2) noise countermeasures in order to maintain 8-bit resolution, attention must be paid to noise on pins av dd and an0 to an7. since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 14-2 in order to reduce noise. . figure 14-2 analog input pin connecting capacitor r20/an0 r21/an1 r22/an2 r23/an3 r24/an4 r25/an5 r26/an6 r27/an7 s/h sample & hold 0 1 aden av dd 8-bit dac ladder resistor adif a/d interrupt successive approximation circuit adr a/d result register address: ed h reset value: undefined 000 001 010 011 100 101 110 111 ads[2:0] an0~an7 100~1000pf analog input
gms81c7008/7016 58 apr., 2001 ver 2.01 (3) ad pin sharing with normal i/o port the analog input pins an0 to an7 also function as input/output port (port r20~r27) pins. when a/d conversion is performed with any of pins an0 to an7 selected, be sure not to execute a port input instruction while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid ap- plying pulses to pins adjacent to the pin undergoing a/d conver- sion. (4) av dd pin input impedance a series resistor string of approximately 10k w is connected be- tween the av dd pin and the av ss pin. therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the av dd pin and the av ss pin, and there will be a large reference voltage error. figure 14-3 a/d converter operation flow figure 14-4 a/d converter control register enable a/d converter a/d start ( adst = 1 ) nop adsf = 1 a/d input channel select analog reference select read adr yes no btcl 76543210 aden - adst a/d status bit analog input channel select initial value: -0-0 0001 b address: 0ec h adcm adsf a/d converter enable bit 0: a/d converter module turn off and current is not flow. 1: enable a/d converter r/w r/w r/w r/w r/w r 000: channel 0 (an0) 001: channel 1 (an1) 010: channel 2 (an2) 011: channel 3 (an3) 100: channel 4 (an4) 101: channel 5 (an5) 110: channel 6 (an6) 111: channel 7 (an7) 0: a/d conversion is in progress 1: a/d conversion is completed a/d start bit setting this bit starts an a/d conversion. after one cycle, bit is cleared to 0 by hardware. ads1 ads0 -ads2 initial value: undefined address: 0ed h adr a/d conversion data btcl 76543210 rrrr rr r r 0: - 1: a/d start --
gms81c7008/7016 apr., 2001 ver 2.01 59 15. serial communication the serial interface is used to transmit/receive 8-bit data serially. serial communication block consists of serial i/o data register, serial i/o mode register, clock selection circuit, octal counter and control circuit as illustrated in figure 15-1.pin r07/sin, r06/ sout and r05/sclk pins are controlled by the serial mode register. the contents of the serial i/o data register can be writ- ten into or read out by software. the serial communication is activated by the instruction set1 siost. the octal counter is reset to 0 by this instruction, starts counting at the falling or rising edge (by pol selection) of the transmit clock (sclk), and it increments at the every clock. a se- rial interrupt request flag is set when the eighth transmit clock signal is input (the serial interface is reset) or when serial commu- nication is discontinued (the octal counter is reset). the data in the serial data register can be shifted synchronously with the transfer clock signal. figure 15-1 sci control register sck1 sck0 sclk/r05 port clock source prescaler divide ratio 0 0 sclk output internal clock ? 4 0 1 sclk output internal clock ? 16 1 0 sclk output internal clock use clock from timer 0 overflow 1 1 sclk input external clock - btcl 76543210 msb pol siost serial transmission status bit serial transmission clock selection initial value: 0000_0001 b address: 0fe h siom siosf msb first or lsb first 0: lsb first 1: msb first r/w r/w r/w r/w r/w r 00: f xin ? 4 01: f xin ? 16 10: timer 0 overflow 11: external clock 0: serial transmission is in progress 1: serial transmission is completed serial transmission start bit setting this bit starts an serial transmission. after one cycle, bit is cleared to 0 by hardware. sck1 sck0 sio1 sio0 r/w serial transmission operation mode 00: normal port(r05,r06,r07) 01: sending mode(sclk,sout,r07) 10: receiving mode(sclk,r06,sin) 11: sending & receiving mode(sclk,sout,sin) initial value: undefined address: 0ff h sior btcl 76543210 r/w r/w r/w r/w r/w r/w r/w r/w sending data during sending mode receiving data during receiving mode selection polarity 0: data in on rising edge, data out on falling edge 1: data in on falling edge, data out on rising edge r/w
gms81c7008/7016 60 apr., 2001 ver 2.01 serial i/o mode register(siom) controls serial i/o function. the pol bit control which edge according to sck1 and sck0, the internal clock or external clock can be selected. serial i/o data register(sior) is an 8-bit shift register. figure 15-2 block diagram of sci 15.1 transmission/receiving timing the serial transmission is started by setting siost(bit1 of siom) to 1. after one cycle of sck, siost is cleared automatically to 0. the serial output data from 8-bit shift register is output at falling edge of sclk. and input data is latched at rising edge of sclk pin. when transmission clock is counted 8 times, serial i/o counter is cleared as 0. transmission clock is halted in h state and serial i/ o interrupt(sioif) occurred. figure 15-3 spi timing diagram at pol=0 r05/sclk pin control circuit r06/sout pin serial io data octal counter serial communication interrupt sioif r07/sin pin sck, sio overflow sck[1:0] mux ? 16 ? 4 11 10 01 00 prescaler f xin f sxin 0x 1x scmr[1:0] t0ov (timer 0 overflow) pol siost start siosf complete clock clear sio1 sio0 [0ff h ] edge detector sio[1:0] shift clock sclk out d1 d2 d3 d4 d6 d7 d0 d5 d1 d2 d3 d4 d6 d7 d0 d5 siost sclk [r05] (pol=0) sout [r06] sin [r07] sioif (interrupt req.) siosf
gms81c7008/7016 apr., 2001 ver 2.01 61 15.2 the method of serial i/o 1. select transmission/receiving mode when external clock is used, the frequency should be less than 1mhz and recommended duty is 50%. 2. in case of sending mode, write data to be send to sior. 3. set siost to 1 to start serial transmission. if both transmission mode is selected and transmission is per- formed simultaneously it would be made error. 4. the sio interrupt is generated at the completion of sio and siosf is set to 1. in sio interrupt service routine, correct trans- mission should be tested. 5. in case of receiving mode, the received data is acquired by reading the sior. figure 15-4 spi timing diagram at pol=1 15.3 the method to test correct transmission figure 15-5 serial method to test transmission d1 d2 d3 d4 d6 d7 d0 d5 d1 d2 d3 d4 d6 d7 d0 d5 siost sclk [r05] (pol=1) sout [r06] sin [r07] sciif siosf serial i/o interrupt service routine se = 0 write siom normal operation overrun error abnormal siosf 0 1 - se : interrupt enable register low ienl(bit3) - sr : interrupt request flag register low irql(bit3) sr 0 1
gms81c7008/7016 62 apr., 2001 ver 2.01 16. buzzer function the buzzer driver block consists of 6-bit binary counter, buzzer register, and clock source selector. it generates square-wave which has very wide range frequency (500hz ~ 250khz at f xin = 4mhz) by user software. a 50% duty pulse can be output to r30/buz pin to use for piezo- electric buzzer drive. pin r30 is assigned for output port of buzz- er driver by setting the bit 5 of pmr (address d9 h ) to 1. at this time, the pin r30 must be defined as output mode (the bit 0 of r3dd=1). example: 2.4khz output at 4mhz. ldm r3dd,#xxxx_xxx1b ldm bur,#0111_0011b set1 pmr.5 ;buz on clr1 pmr.5 ;buz off x means dont care the bit 0 to 5 of bur determines output frequency for buzzer driving. equation of frequency calculation is shown below. f buz : buzzer frequency f xin : oscillator frequency divide ratio: prescaler divide ratio by buck[1:0] bur: lower 6-bit value of bur. buzzer period value. the frequency of output signal is controlled by the buzzer control register bur.the bur[5:0] determine output frequency for buzzer driving. figure 16-1 block diagram of buzzer driver figure 16-2 pmr and buzzer register f buz f xin 2 divideratio bur 5:0 [] 1 + () --------------------------------------------------------------------------------------- - = prescaler ? 8 ? 32 ? 16 ? 64 r30/buz pin pmr.5 r30 port data 0 1 f/f ? 2 comparator 6-bit compare data 6-bit binary counter mux 00 01 10 11 bur[5:0] [0fd h ] bur[7:6] f xin f sxin 0x 1x scmr[1:0] bur[5:0] bur address: 0fd h reset value: undefined w wwww w source clock select 00: ? 8 01: ? 16 10: ? 32 11: ? 64 define frequency of buzzer signal ww buck1 buck0 r30/buz selection pmr address: 0d9 h reset value: 00 h r/w r/w r/w r/w r/w r/w 0: r30 port (turn off buzzer) r/w r/w pwm1 buz pwm0 int0 int1 int2 ec0 ec2 1: buz port (turn on buzzer)
gms81c7008/7016 apr., 2001 ver 2.01 63 note that bur is a write-only register. the 6-bit counter is cleared and starts the counting by writing sig- nal at bur register. it is incremental from 00 h until it matches 6- bit bur value. when main-frequency is 4mhz, buzzer frequency is shown as below table. the unit is khz. bur [5:0] buck[1:0] bur [5:0] buck[1:0] 00 01 10 11 00 01 10 11 00 01 02 03 04 05 06 07 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 20 21 22 23 24 25 26 27 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 08 09 0a 0b 0c 0d 0e 0f 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 28 29 2a 2b 2c 2d 2e 2f 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 10 11 12 13 14 15 16 17 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 30 31 32 33 34 35 36 37 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 18 19 1a 1b 1c 1d 1e 1f 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977 38 39 3a 3b 3c 3d 3e 3f 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.906 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488 table 16-1 buzzer frequency at 4mhz
gms81c7008/7016 64 apr., 2001 ver 2.01 17. interrupts the gms81c7008/16 interrupt circuits consist of interrupt en- able register (ienh, ienl), interrupt request flags of irqh, irql, priority circuit, and master enable flag (i flag of psw). thirteen interrupt sources are provided. the configuration of in- terrupt circuit is shown in figure 17-2. the keyscan interrupt is generated when 1-to-0 transition is de- tected at ks0 or ks0 pin. the basic interval timer interrupt is generated by bitif which is set by an overflow in the timer register. the watchdog timer interrupt is generated by wdtif which set by a match in watchdog timer register. the external interrupts int0 ~ int2 each can be transition-acti- vated (1-to-0 or 0-to-1 transition) by selection ieds. the flags that actually generate these interrupts are bit int0if, int1if and int2if in register irqh and irql. when an exter- nal interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. the timer 0 ~ timer 3 interrupts are generated by t0if~t3if which are set by a match in their respective timer/counter register. the serial communication interrupts are generated by sioif which is set by 8-bit serial data transmitting or receiving through sck, sin, sout pin. the ad converter interrupt is generated by adif which is set by finishing the analog to digital conversion. the watch timer interrupt is generated by wtif which is set by an 14-bit binary counter overflow. the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw on page 19), the interrupt enable register (ienh, ienl), and the interrupt request flags (in irqh and irql) except power-on reset and software brk interrupt. below table shows the interrupt priority. vector addresses are shown in figure 8-6 on page 21. interrupt enable registers are shown in figure 17-3. these registers are composed of interrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. when enable flag is 0, a corresponding interrupt source is prohibited. note that psw contains also a master enable bit, i- flag, which disables all interrupts at once. figure 17-1 interrupt request flag reset/interrupt symbol priority hardware reset key scan interrupt basic interval timer watchdog timer external interrupt 0 external interrupt 1 timer/counter 0 timer/counter 1 external interrupt 2 serial communication adc interrupt watch timer interrupt timer/counter 2 timer/counter 3 reset ks bit wdt int0 int1 timer 0 timer 1 int2 sci adc wt timer 2 timer 3 - 1 2 3 4 5 6 7 8 9 10 11 12 13 wdtif r/w - timer/counter 3 initial value: -000 0000 b address: 0dd h irqh ksif msb lsb t0if t1if int0if int1if bitif r/w r/w timer/counter 2 timer/counter 1 interrupt request flag external interrupt 1 serial communication initial value: 0--0 0000 b address: 0dc h irql msb lsb timer/counter 0 r/w r/w -r/w r/w basic interval timer watchdog timer a/d converter external interrupt 0 key scan sioif - int2if - t2if t3if adif wtif - r/w r/w r/w r/w r/w - r/w watch timer external interrupt 2
gms81c7008/7016 apr., 2001 ver 2.01 65 . figure 17-2 block diagram of interrupt figure 17-3 interrupt enable flag int1 int0 int2 int2if ienl interrupt enable interrupt enable irql [0dc h ] irqh [0dd h ] interrupt vector address generator internal bus line register (higher byte) internal bus line register (lower byte) release stop to cpu interrupt master enable flag i-flag ienh priority control i-flag is in psw, it is cleared by di, set by ei instruction. when it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by reti instruction, i-flag is set to 1 by hardware. [0da h ] [0db h ] int0if int1if t3if t2if timer 3 timer 2 a/d converter adif sioif bitif watchdog timer serial bit wdtif communication watch timer wtif key scan ksif t1if t0if timer 1 timer 0 sioe int2e timer/counter 3 interrupt enable flag initial value: 0--0 0000 b address: 0da h ienl - msb lsb t2e t3e ade wte - r/w r/w timer/counter 2 interrupt enable flag watch timer interrupt enable flag serial communication interrupt enable flag initial value: -000 0000 b address: 0db h ienh msb lsb r/w r/w r/w - r/w basic interval timer interrupt enable flag watchdog timer interrupt enable flag a/d converter interrupt enable flag external interrupt 2 enable flag 0: disable 1: enable value wdte r/w - kse t0e t1e int0e int1e bite r/w r/w r/w r/w -r/w r/w - timer/counter 1 interrupt enable flag timer/counter 0 interrupt enable flag external interrupt 1 enable flag external interrupt 0 enable flag key scan interrupt enable flag
gms81c7008/7016 66 apr., 2001 ver 2.01 17.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to 0 by a reset or an instruction. inter- rupt acceptance sequence requires 8 f xin (2 m s at f main =4.19mhz) after the completion of the current instruction execution. the interrupt service task is terminated upon execu- tion of an interrupt return instruction [reti]. interrupt acceptance 1. the interrupt master enable flag (i-flag) is cleared to 0 to temporarily disable the acceptance of any follow- ing maskable interrupts. when a non-maskable inter- rupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to 0. 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack pointer decreases 3 times. 4. the entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. the instruction stored at the entry address of the inter- rupt service program is executed. figure 17-4 timing chart of interrupt acceptance and interrupt return instruction a interrupt request is not accepted until the i-flag is set to 1 even if a requested interrupt has higher priority than that of the current interrupt being serviced. when nested interrupt service is required, the i-flag should be set to 1 by ei instruction in the interrupt service program. in this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. saving/restoring general-purpose register during interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. these regis- ters are saved by the software if necessary. also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. the following method is used to save/restore the general-purpose registers. v.l. system clock address bus pc sp sp-1 sp-2 v.h. new pc v.l. data bus not used pch pcl psw adl op code adh instruction fetch internal read internal write interrupt processing step interrupt service task v.l. and v.h. are vector addresses. adl and adh are start addresses of interrupt service routine as vector contents. watch timer 012 h 0e3 h 0ffe4 h 0ffe5 h 0e h 2e h 0e312 h 0e313 h entry address correspondence between vector table address for watch timer interrupt and the entry address of the interrupt service program. vector table address
gms81c7008/7016 apr., 2001 ver 2.01 67 example: register save using push and pop instructions general-purpose register save/restore using push and pop instruc- tions; 17.2 brk interrupt software interrupt can be invoked by brk instruction, which has the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk inter- rupt is generated, b-flag of psw is set to distinguish brk from tcall 0. each processing step is determined by b-flag as shown in figure 17-5. figure 17-5 execution of brk/tcall0 17.3 multi interrupt if two requests of different priority levels are received simulta- neously, the request of higher priority level is serviced. if re- quests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hard- ware which request is serviced. however, multiple processing through software for special fea- tures is possible. generally when an interrupt is accepted, the i- flag is cleared to disable any further interrupt. but as user sets i- flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. example: during timer1 interrupt is in progress, int0 interrupt serviced without any suspend. timer1: push a push x push y ldm ienh,#08h ; enable int0 only ldm ienl,#00h ; disable other ei ; enable interrupt : : : : ldm ienh,#0ffh ; enable all interrupts ldm ienl,#0ffh pop y pop x pop a reti . figure 17-6 execution of multi interrupt intxx: push a push x push y ;save acc. ;save x reg. ;save y reg. interrupt processing pop y pop x pop a reti ;restore y reg. ;restore x reg. ;restore acc. ;return main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return b-flag brk interrupt routine reti tcall0 routine ret brk or tcall0 =0 =1 enable int0 timer 1 service int0 service main program service occur timer1 interrupt occur int0 ei disable other enable int0 enable other in this example, the int0 interrupt can be serviced without any pending, even timer1 is in progress. because of re-setting the interrupt enable registers ienh,ienl and master enable ei in the timer1 routine.
gms81c7008/7016 68 apr., 2001 ver 2.01 17.4 external interrupt the external interrupt on int0, int1 and int3 pins are edge triggered depending on the edge selection register ieds (address 0d8 h ) as shown in figure 17-7. the edge detection of external interrupt has three transition acti- vated mode: rising edge, falling edge, and both edge. figure 17-7 external interrupt block diagram int0 ~ int2 are multiplexed with general i/o ports (r00~r02). to use as an external interrupt pin, the bit of port mode register pmr should be set to 1 correspondingly as shown in figure 17- 9. example: to use as an int0 and int2 : : ; **** set port as an input port r00,r02 ldm r0dd,#1111_1010b ; ; **** set port as an external interrupt port ldm pmr,#05h ; ; **** set falling-edge detection ldm ieds,#0001_0001b : : response time the int0 ~ int2 edge are latched into int1if ~ int2if at every machine cycle. the values are not actually polled by the circuitry until the next machine cycle. if a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be ex- ecuted. the div itself takes twelve cycles. thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. figure 17-8 shows interrupt response timings. figure 17-8 interrupt response timing diagram 17.5 key scan interrupt gms81c7008/16 has the key-scan block which consists of port selection multiplexer, interrupt controller, key scan mode register and falling edge detector shown as figure 17-10. when the key scan interrupt is used, key scan register ksmr (address 0f0 h ) should be set to 1 as ks0 and ks1. after reset, initial setting is general r10 and r00 ports. if key scan is detected at any one or more of these pins, the ksif request flag is set to 1. this generates an interrupt request. it also can be used in the way of release from stop mode. int0if int0 pin int0 interrupt int1if int1 pin int1 interrupt int2if int2 pin int2 interrupt ieds [0d8 h ] edge selection register 2 2 2 interrupt goes active interrupt latched interrupt processing interrupt routine 8 f xin period max. 12 f xin period
gms81c7008/7016 apr., 2001 ver 2.01 69 figure 17-9 pmr and ieds registers . figure 17-10 key scan port block diagram btcl buz pwm0 pwm1 int1s 0: r00 1: int0 initial value: 00 h address: 0d9 h pmr ec2s int0s int2s ec0s 0: r01 1: int1 0: r02 1: int2 0: r03 1: ec0 0: r32 1: pwm1/t3o 0: r31 1: pwm0/t1o 0: r30 1: buz 0: r04 1: ec2 lsb msb btcl - - r/w r/w r/w r/w r/w r/w ied2h - -ied0h initial value: 00 h address: 0d8 h ieds ied2l ied0l ied1l ied1h lsb msb edge selection register 00: reserved 01: falling (1-to-0 transition) 10: rising (0-to-1 transition) 11: both (rising & falling) int0 int1 int2 r/w r/w r/w r/w r/w r/w r/w r/w key scan interrupt r10/ks0 r11/ks1 ksif v dd ksmr [0f0 h ] r1pu[1:0] key scan mode register ksmr address: 0f0 h reset value: 00 h - ---- - ks1 ks0 port selection 0: r10 1: ks0 port selection 0: r11 1: ks1 reserved edge detector pull up resistor typ. 160k w
gms81c7008/7016 70 apr., 2001 ver 2.01 18. lcd driver the gms81c7008/16 has the circuit that directly drives the liq- uid crystal display (lcd) and its control circuit. in addition, vcl n pin is provided as the drive power pin. basically, the gms81c7008/16 has 24 seg. 4 com. ports of lcd driver. extend display modes are shown in left table. figure 18-1shows the configuration of the lcd driver. ********caution******** when you developing the software using by emulator, you must select the external bias re- sistor mode because of no internal bias resistor inside the emulator (eva. chip). figure 18-1 lcd driver block diagram 18.1 lcd control registers the lcd driver is controlled by the lcd control register lcr which is shown in figure 18-2. lcd block input the clock from gms81c7008/16 1/4 duty: 24 seg 4com 1/3 duty: 25 seg 3com 1/2 duty: 26 seg 2com static: 27 seg 1com seg0/r40 display data select control display data buffer register r4 or segment lcd display memory segment driver common driver (27 4 bits) ? 32 ? 64 ? 128 ? 256 timing control seg7/r47 lpmr[1:0] lpmr[3:2] seg8/r50 seg15/r57 lpmr[5:4] seg16/r60 seg23/r67 select seg or normal port [0f1 h ] lcr internal bus line enable lcd control bias voltage and resistor by lpmr [0f2 h ] mux same with above same with above wtck[1:0] mux f sub f main ? 2 7 00 01 prescaler com0 com1/seg26 com2/seg25 com3/seg24 lcr[3:2] of address 0f1 h com. or seg. power & bias control bias vcl2 vcl1 vcl0 control frame frequency
gms81c7008/7016 apr., 2001 ver 2.01 71 the watch timer. when lcd is operate, the watch timer much be enabled by wten (bit 6 of address 0ef h ). figure 18-2 lcd control register 76543210 selection frame frequency 00: 1024hz 01: 512hz 10: 256hz 11: 128hz initial value: 00 h address: 0f1 h lcr r/w r/w r/w duty control 00: 1/4 duty 01: 1/3 duty (seg24 active) bias resistor control 0: external 1: internal lcd display control 0: lcd display all segment 0 data output 1: lcd display enable r/w r/w r/w bias transistor control 0: off 1: on btc subm lcden brc lck1 lck0 r/w r/w 10: 1/2 duty (seg24, seg25 active) 11: static (seg24, seg25, seg26 active) sub clock port mode 0: sxin, sxout 1: r35, r36 dty0 dty1 76543210 r4 port selection 00:seg0~seg7 01:seg4~seg7,r40~r43 10:seg0~seg3,r44~r47 11:r40~r47 initial value:0000 0000 address: 0f2 h lpmr r/w r/w r/w r/w r5lpmr r4lpmr r5 port selection 00:seg8~seg15 01:seg12~seg15,r50~r53 10:seg8~seg11,r54~r57 11:r50~r57 r6lpmr r6 port selection 00:seg16~seg23 01:seg20~seg23,r60~r63 10:seg16~seg19,r64~r67 11:r60~r67 r/w r/w r/w r/w -- 76543210 initial value: 00 h address: 0f3 h rpr r/w r/w - rpr1 rpr0 - - - - - -- - - - - the rpr register is used for ram page selection. ram page instruction prp1 prr0 page 0 clrg x x page 0 setg 0 0 page 1 setg 0 1 reserved setg 1 0 reserved setg 1 1 when f sxin = 32.768khz f xin = 4.19mhz no internal bias registers in the emulator, so user must select the 0, external mode at least during use the emulator. otp and mask mcu can use both.
gms81c7008/7016 72 apr., 2001 ver 2.01 18.2 duty and bias selection of lcd driver 5 kinds of driving methods can be selected by dty (bits 3 and 2 of lcd control register and connection of vcl pin externally. figure 18-3 shows typical driving waveforms for lcd.). figure 18-3 lcd drive waveform (voltage com-seg pins) 18.3 selecting frame frequency frame frequency is set to the base frequency as shown in the fol- lowing table 18-1. the lck[1:0] of lcr determines the frequency of com signal scanning of each segment output. the watch timer must be en- abled when the lcd display is turned on. reset clears the lcd control register lcr values to logic zero. the lcd display can continue to operate even during the sleep and stop modes if a sub-frequency clock is oscillate and used as clock source of lcd driver. . vcl2 vcl1 vcl0 gnd -vcl0 -vcl1 -vcl2 1/f f data 1 (a) 1/4 duty, 1/3 bias data 0 vcl2 vcl1 vcl0 gnd -vcl0 -vcl1 -vcl2 1/f f data 1 (b) 1/3 duty, 1/3 bias data 0 1/f f data 1 data 0 (c) 1/2 duty,1/3 bias 1/f f data 1 data 0 vcl2 vcl1 vcl0 gnd -vcl0 -vcl1 -vcl2 (e) static note: f f : lcd frame frequency 1/f f data 1 data 0 vcl2 gnd -vcl0 = -vcl1 -vcl2 (d) 1/2 duty, 1/2 bias vcl1 = vcl0 vcl2 vcl1 vcl0 gnd -vcl0 -vcl1 -vcl2 lck[1:0] lcd clock frame frequency (hz) (when f sub = 32.768 khz) 00 01 10 11 f sub ? 32 f sub ? 64 f sub ? 128 f sub ? 256 1024 512 256 128 table 18-1 setting of lcd frame frequency
gms81c7008/7016 apr., 2001 ver 2.01 73 lcd port selection segment pins are also used for normal i/o pins. the lcd port se- lection register lpmr is used to set r n pin for ordinary digital in- put. refer to lpmr register as shown in figure 18-2. bias resistor to operate lcd, built-in bias resistor dividing v dd to v ss section into several stages generates necessary voltage. the btc (bit 6 of lcr) switches transistor supplying voltage to serially connected bias resistor. if it is 1, it turns on, and if it is 0, it turns off. the lcd drive voltage (v cl2 ) is given by the dif- ference in potential (v dd -v cl2 ) between pins v dd and v cl2 . therefore, when the mcu operating voltage is 5v and lcd drive voltage are the same, the bias pin is connected to the v cl2 pin as shown in (a) of figure 18-5. figure 18-4 application example of 5v lcd panel when require supply 3v output to the lcd, the voltage of v cl2 becomes 3v as shown in figure 18-5. because v dd is down to 3v through internal 2r resistor. the lcd light only when the difference in potential between the segment and common output is vcl, and turn off at all other times. during reset, the power switch of the lcd driver is turned off automatically, shutting off the vcl voltage. one frame (at 1/4 duty, 1/3 bias) com0 pin vcl1 vcl2 bias btc v dd v ss (a) internal, static or 1/3 bias btc = 1 brc = 1 internal bias resistors mcu internal vcl0 brc 2r r r r btc v dd v ss (b) internal, static or 1/2 bias btc = 1 brc = 1 two pins are connected each other internal bias resistors mcu internal brc 2r r r r typ. r=65k w vcl1 vcl2 bias vcl0 short two pins each other externally vcl2=5v vcl1=3.33v vcl0=1.67v vcl2=5v vcl1=2.5v vcl0=2.5v
gms81c7008/7016 74 apr., 2001 ver 2.01 figure 18-5 application example of 3v lcd panel some user want to use external bias resisor instead of internal, you can connect external resistor as shown in figure 18-6. and the external capacitors are may required for stable display accord- ing to your system environment. figure 18-6 external resistor vcl1 vcl2 bias btc v dd = 5v v ss (a) internal, static or 1/3 bias btc = 1 brc = 1 short two pins externally internal bias resistors mcu internal vcl0 brc 2r r r r typ. r=65k w btc v dd = 5v v ss (b) internal, static or 1/2 bias btc = 1 brc = 1 internal bias resistors mcu internal brc 2r r r r typ. r=65k w vcl1 vcl2 bias vcl0 vcl2=3v vcl1=2v vcl0=1v vcl2=3v vcl1=1.5v vcl0=1.5v vcl1 vcl2 bias btc v dd v ss btc = 0 brc = 0 external circuit internal bias resistors mcu internal vcl0 brc 2r r r r v ss v dd adjust contrast
gms81c7008/7016 apr., 2001 ver 2.01 75 18.4 lcd display memory display data are stored to the display data area (address 100 h -11a h ) in the data memory. the display data stored to the display data area are read au- tomatically and sent to the lcd driver by the hardware. the lcd driver generates the segment signals and com- mon signals in accordance with the display data and drive method. figure 18-7 lcd display memory therefore, display patterns can be changed by only over- writing the contents of the display data area with a pro- gram. the table look up instruction is mainly used for this overwriting. figure 18-7 shows the correspondence between the display data area and the seg/com pins. the lcd lights when the display data is 1 and turn off when 0. the number of segment which can be driven differs de- pending on the lcd drive method, therefore, the number of display data area bits used to store the data also differs (refer to figure 18-2). consequently, data memory not seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 com0 com1 com2 com3 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 012345 67 bit 100 h 101 h 102 h 103 h 104 h 105 h 106 h 107 h 108 h 109 h 10a h 10b h 10c h 10d h 10e h 10f h 110 h 111 h 112 h 113 h 114 h 115 h 116 h 117 h 118 h 119 h 11a h note: the bit 4 to 7 of every byte are reserved. any read or write is not effect. drive methods bit 3 bit 2 bit 1 bit 0 1/4 duty com3 com2 com1 com0 1/3 duty - com2 com1 com0 1/2 duty - - com1 com0 static --- com0 table 18-2 the duty vs. com port configuration
gms81c7008/7016 76 apr., 2001 ver 2.01 used to store display data and data memory for which the address are not connected to lcd can be used to store or- dinary users processing data. blanking blanking is applied by setting lcden (bit 7 of lcr) to 0 and turns off the lcd by outputting the non light operation level to the com pin. when setting frame frequency or changing operat- ing mode, lcd display should be off before operation, to prevent display flickering. 18.5 control method of lcd driver initial setting flow chart of initial setting is shown in figure 18-8. example: when operating with 1/4 duty lcd using a frame frequency of 512hz. . figure 18-8 initial setting of lcd driver figure 18-9 example of connection com & seg display data setting normally, display data are kept permanently in the pro- gram memory and then stored at the display data area by the table look-up instruction. this can be explained using numerical display with 1/4 duty lcd as an example. the com and seg connections to the lcd and display data are the same as those shown is figure 18-9. programming ldm lcr,#0101_0001b ;1/4duty, f f =512hz (f sub = 32.768khz) : setg ldm rpr,#1 ;select lcd memory ;area (page 1 = address 1xx h ) ldx #0 c_lcd1: lda #0 ;ram clear ;ram(100h~11ah) sta {x}+ cmpx #01bh bne c_lcd1 clrg : : set1 lcr.5 ;enable lcd display : : clear lcd display memory select frame frequency turn on lcd setting of lcd drive method initialize of display memory enable display (release of blanking) seg0 seg1 com3 com0 com1 com2 example: display 2 11 10 01 01 ** ** ** ** 100 h 101 h 31 20 bit 7 5 64 note: * are dont care.
gms81c7008/7016 apr., 2001 ver 2.01 77 example for displaying character is shown below. note: when power on reset, sub oscillation start up time is required. enable lcd display after sub oscillation is sta- bilized, or lcd may occur flicker at power on time shortly. : clrg ldx #dispram golcd: lda {x} tay lda !font+y ;load font data ldm rpr,#1 ;set rpr = 1 to access lcd setg ;set page 1 ldx #0 sta {x}+ ;lower 4 bits of acc. -> m(x) xcn sta {x} ;upper 4 bits of acc. -> m(x+1) clrg ;set page = 0 : : font db 1101_0111b ; 0 db 0000_0110b ; 1 db 1110_0011b ; 2 db 1010_0111b ; 3 db 0011_0110b ; 4 db 1011_0101b ; 5 db 1111_0101b ; 6 db 0000_0111b ; 7 db 1111_0111b ; 8 db 0011_0111b ; 9 font data write into the lcd memory
gms81c7008/7016 78 apr., 2001 ver 2.01 19. watch / watchdog timer 19.1 watch timer the watch timer goes the clock continuously even during the power saving mode. when mcu is in the stop or sleep mode, mcu can wake up itself every 2hz or 4hz or 16hz. the watch timer consists of input clock selector, 14-bit binary counter, interval selector and watch timer mode register wtmr (address 0ef h ). the wtmr is 5-bit read/write register and shown in figure 19-2. wtmr can select the clock input by 2 bits wtck[1:0] and interval time selector by 2 bits wtin[1:0] and enable/disable bit. the wten bit is set to 1 timer start counting. input clocks can be selected among three different source which are sub clock or divided main clock (f xin ? 128) or main clock. for the switching between main and sub clock, rec- ommend the oscillator 4.194304mhz as a main and 32.768khz as a sub. because above main frequency is equal to 128 times of sub frequency. generally main clock (f xin ) at wtck=10 b is not be used, it is just for test purpose in factory. in the stop mode, the main clock is stopped but sub clock is os- cillation continuously for watch clock operation. output timer in- terval can be selected and watch timer interrupt is generated. ldm ienl,#xxxx_x1xxb ei ldm wtmr,#0100_1000b figure 19-1 block diagram of watchdog timer 19.2 watchdog timer the watchdog timer rapidly detects the cpu malfunction such as endless looping caused by noise or the like, and resumes the cpu to the normal state. the watchdog timer signal for detecting malfunction can be se- lected either a reset cpu or a interrupt request as you want. when the watchdog timer is not being used for malfunction de- tection, it can be used as a timer to generate an interrupt at fixed intervals. watchdog timer control figure 19-2 shows the watchdog timer control register wdtr (address 0df h ). the watchdog timer is automatically enabled initially and watchdog output to reset cpu but clock input source is disabled. to enable this function, you should write bit wten of wtmr (address 0ef h ) set to 1. the cpu malfunction is detected during setting of the detection time, selecting of output, and clearing of the binary counter. clearing the 2-bit binary counter by bit wdclr of wdtr is re- peated within the detection time. if the malfunction occurs for any cause, the watchdog timer out- put will become active from the binary counters unless the binary counter is cleared. at this time, when wdom=1, a reset is gen- erated, which drives the reset pin to low to reset the internal hardware. when wdom=0, a watchdog timer interrupt (wd- tif) is generated instead of reset function. this interrupt can be used general timer as user want. when main clock is selected as clock input source on the stop mode, clock input is stopped so the watchdog timer temporarily stops counting. the other side, when sub clock is selected as clock input source on the stop mode, sub clock operates always enable watch timer interrupt wtif 0 1 14-bit binary counter mux f sxin f xin ? 128 f xin f w f sxin = 32.768 khz f xin = 4.194304 mhz interval selector 2hz 4hz 16hz 2hz 4hz 8hz 16hz 2-bit binary counter wdck[1:0] wtin[1:0] wtck[1:0] wdoe[0df h ] r34/wdto clear 0: stop 1: clear and start wdclr wdtif to reset cpu watchdog timer interrupt overflow wden wdom 00 01 10 00 01 10 11 00 01 10 enable 0 1 wten mux when
gms81c7008/7016 apr., 2001 ver 2.01 79 so the watchdog timer works continuously. figure 19-2 wtmr, wdtr: watch timer and watchdog timer data register example: sets the watchdog timer detection time to 1 sec at 4.19mhz, 32.768khz enable and disable watchdog watchdog timer is enabled by setting wden (bit 4 in ckctlr) to 1. wden is initialized to 1 during reset and it should be clear to 0 disable. example: enables watchdog timer for reset : ldm wtmr,#0100_xxxxb; wten ? 1 ldm wdtr,#00x1_xx11b; wden ? 1 : the watchdog timer is disabled by clearing either bit 4 (wden) of wdtr or bit 6 (wten) of wtmr. the watchdog timer is halted in stop mode and restarts automatically after stop mode is released. clearing 2-bit binary counter of the watchdog timer the watchdog timer count the clock source as 14-bit binary initial value: -0--_0000 b address: 0ef h wtmr - - wten wtin1 wtin0 -r/w r/w r/w -r/w r/w -- wtck1 wtck0 clock source selection 00: sub clock 01: main clock (f xin ? 128) 10: main clock (test purpose in factory) 11: - watch timer interrupt interval selection 00: 16hz 01: 4hz 10: 2hz 11: - watch timer count enable 0: disable 1: enable initial value: --01_0010 b address: 0df h wdtr - wdoe wdck1 wdck0 r/w r/w r/w --r/w - wden wdom wdclr watchdog timer interrupt interval selection 00: 2 sec. 01: 1 sec. 10: 0.5 sec. 11: 0.25 sec. r34/wdto selection 0: r34 port 1: wdto port r/w r/w clear bit 0: normal operation 1: clear and starts counting when f sxin = 32.768khz f xin = 4.19mhz output mode 0: interrupt request 1: reset cpu watchdog timer count enable 0: disable 1: enable when f sxin = 32.768khz f xin = 4.19mhz ldm wtmr,#0100_1000b ; select sub clock as an input source ldm wdtr,#0001_0111b set1 wdclr ; clear counter : : : : set1 wdclr ; clear counter : : : : set1 wdclr ; clear counter within 0.75 sec. within 0.75 sec.
gms81c7008/7016 80 apr., 2001 ver 2.01 counter which is free run can not be cleared. the watchdog timer has 2-bit binary counter. it is incremented by 14-bit binary counter match as shown in figure 19-1. interrupt request flag or reset signal are generated by overflow 2-bit binary counter. during normal operation in the software, 2-bit binary counter should be cleared by bit wdclr of wdtr within watchdog timer overflow. the time of clearing must be within 3 times of 14-bit binary counter interval as shown in figure 19-3. the worst case, watchdog time is just 3 times of 14-bit counter. figure 19-3 watchdog timer timing if the watchdog timer output becomes active, a reset is generated, which drives the reset pin low to reset the internal hardware. the main clock oscillator also turns on when a watchdog timer re- set is generated in sub clock mode. 14-bit binary 2-bit binary wdtif interrupt write wdclr = 1 at this point 10 counter clear n counter r34/wdto pin reset 0 1 1ffe ~ ~ ~ ~ 1fff counter 0 23 01 1ffe 1fff 01 1ffe 1fff ~ ~ ~ ~ 01 1ffe 1fff 2 222 ~ ~ ~ ~ 8 osc. (2us at f xin =4.19mhz) even if user set to 1 sec., when wdtr = 0011_0111b worst case 0.75 second
gms81c7008/7016 apr., 2001 ver 2.01 81 20. power down operation the gms81c7008/16 has two power-down modes. in power- down mode, power consumption is reduced considerably that in battery operation battery life can be extended a lot. sleep mode is entered by setting bit 0 of sleep mode reg- ister, and stop mode is entered by stop instruction. 20.1 sleep mode in this mode, the internal oscillation circuits remain active. oscillation continues and peripherals are operate normally but cpu stops. movement of all peripherals is shown in table 20-1. sleep mode is entered by setting bit 0 of smr (address 0de h ). it is released by reset or interrupt. to be release by interrupt, interrupt should be enabled before sleep mode. figure 20-1 sleep mode register figure 20-2 sleep mode release timing by external interrupt . figure 20-3 sleep mode release timing by reset pin sleep mode register smr address : 0de h reset value : -------0 0: release sleep mode 1: enter sleep mode w oscillator normal operation stand-by mode normal operation interrupt internal cpu clock release set bit 0 of smr (x in or sx in pin) ~ ~ ~ ~ oscillator (x in or sx in pin) 0 bit counter 1 fe ff 0 12 ~ ~ t st = 62.5ms ~ ~ ~ ~ reset internal cpu clock clear & start ~ ~ ~ ~ normal operation sleep mode normal operation release set bit 0 of smr ~ ~ ~ ~ ~ ~ at 4.19mhz by hardware ~ ~ 2 t st = x 256 f main ? 1024 1
gms81c7008/7016 82 apr., 2001 ver 2.01 20.2 stop mode for applications where power consumption is a critical factor, device provides reduced power of stop. start the stop operation an instruction that stop causes to be the last instruction is executed before going into the stop mode. in the stop mode, the on-chip main-frequency oscillator is stopped. with the clock frozen, all functions are stopped, but the on- chip ram and control registers are held. the port pins output the values held by their respective port data register, the port direction registers. the status of peripherals during stop mode is shown below. note: since the x in pin is connected internally to gnd to avoid current leakage due to the crystal oscillator in stop mode, do not use stop instruction when an external clock is used as the main system clock. in the stop mode of operation, v dd can be reduced to minimize power consumption. be careful, however, that v dd is not re- duced before the stop mode is invoked, and that v dd is restored to its normal operating level before the stop mode is terminated. the reset should not be activated before v dd is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. and after stop instruction, at least two or more nop instruction should be written as shown in example below. example) ldm ckctlr,#0eb ;32.8ms ; ldm ckctlr,#0fb ;65.5ms stop nop nop : the interval timer register ckctlr should be initialized (0f h or 0e h ) by software in order that oscillation stabilization time should be longer than 20ms before stop mode. release the stop mode the exit from stop mode is using hardware reset or external in- terrupt, watch timer, key scan or timer/counter. to release stop mode, corresponding interrupt should be enabled before stop mode. specially as a clock source of timer/event counter, ec0 or ec2 pin can release it by timer/event counter interrupt request reset redefines all the control registers but does not change the on-chip ram. external interrupts allow both on-chip ram and control registers to retain their values. start-up is performed to acquire the time for stabilizing oscilla- tion. during the start-up, the internal operations are all stopped. peripheral stop mode sleep mode cpu all cpu operations are disabled all cpu operations are disabled ram retain retain lcd driver lcd driver operates continuously lcd driver operates continuously basic interval timer halted bit operates continuously timer/event counter halted (only when the event counter mode is enabled, timer operates normally) timer/event counter operates continuously watch timer watch timer operates continuously watch timer operates continuously main-oscillation stop (x in pin = l, x out pin = l) oscillation sub-oscillation oscillation oscillation i/o ports retain retain control registers retain retain release method reset, key scan interrupt, sio interrupt, watch timer interrupt, timer interrupt (ec0,2), external interrupt reset, all interrupts table 20-1 peripheral operation during power down mode
gms81c7008/7016 apr., 2001 ver 2.01 83 figure 20-4 stop mode release timing by external interrupt figure 20-5 stop mode release timing by reset minimizing current consumption the stop mode is designed to reduce power consumption. to minimize current drawn during stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. note: in the stop operation, the power dissipation asso- ciated with the oscillator and the internal hardware is low- ered; however, the power dissipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level becomes higher than the power voltage level (by approximately 0.3v), a cur- rent begins to flow. therefore, if cutting off the output tran- sistor at an i/o port puts the pin signal into the high- impedance state, a current flow across the ports input tran- sistor, requiring it to fix the level by pull-up or other means. before executing stop instruction, basic interval timer must be set oscillator (x in pin) ~ ~ n 0 bit counter n+1 n+2 n+3 ~ ~ normal operation stop operation normal operation 1 fe ff 0 12 ~ ~ ~ ~ ~ ~ t st > 20ms ~ ~ ~ ~ external interrupt internal clock clear stop instruction executed ~ ~ ~ ~ ~ ~ properly by software to get stabilization time which is longer than 20ms. by software ~ ~ oscillator (x in pin) ~ ~ n 0 bit counter n+1 n+2 n+3 ~ ~ normal operation stop operation normal operation 1 fe ff 0 12 ~ ~ ~ ~ ~ ~ t st > 62.5ms internal clock clear stop instruction executed ~ ~ ~ ~ ~ ~ at 4.19mhz by hardware ~ ~ reset n+2 t st = x 256 f main ? 1024 1 ~ ~ ~ ~
gms81c7008/7016 84 apr., 2001 ver 2.01 it should be set properly that current flow through port doesn't ex- ist. first consider the setting to input mode. be sure that there is no current flow after considering its relationship with external cir- cuit. in input mode, the pin impedance viewing from external mcu is very high that the current doesnt flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if un-firmed voltage level (not v ss or v dd ) is applied to input pin, there can be little current (max. 1ma at around 2v) flow. if it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. setting to high or low is decided considering its relationship with external circuit. for example, if there is external pull-up resistor then it is set to output mode, i.e. to high, and if there is external pull-down register, it is set to low. figure 20-6 application example of unused input port figure 20-7 application example of unused output port input pin v dd gnd i v dd x weak pull-up current flows v dd internal pull-up input pin i v dd x very weak current flows v dd o o open open i=0 o i=0 o gnd when port is configure as an input, input level should be closed to 0v or 5v to avoid power consumption. output pin gnd i in the left case, much current flows from port to gnd. x on off output pin gnd i in the left case, tr. base current flows from port to gnd. i=0 x off on v dd l on off open gnd v dd l on off to avoid power consumption, there should be low output on off o o v dd o to the port .
gms81c7008/7016 apr., 2001 ver 2.01 85 21. oscillator circuit the gms81c7008/16 has two oscillation circuits internally. x in and x out are input and output for main frequency and sx in and sx out are input and output for sub frequency, respectively, in- verting amplifier which can be configured for being used as an on-chip oscillator, as shown in figure 21-1. to use rc oscillation instead of crystal, user should check mark on the "a. mask or- der sheet" on page i of the appendix of this manual. however in the otp device, when the programming rc oscillation can be selected or not into the configuration bit. for more detail, refer to "24.1 otp programming" on page 89. note: when using the sub clock oscillation, connect a re- sistor in series with r which is shown as below figure. in order to reduce the power consumption, the sub clock oscillator employs a low amplification factor circuit. be- cause of this, the sub clock oscillator is more sensitive to noise than the main system clock oscillator. figure 21-1 oscillation circuit oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. since each crystal and ceramic res- onator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external compo- nents. oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. since each crystal and ceramic res- onator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external compo- nents. in addition, see figure 21-2 for the layout of the crystal. note: minimize the wiring length. do not allow the wiring to intersect with other signal conductors. do not allow the wir- ing to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground it to any ground pattern where high cur- rent is present. do not fetch signals from the oscillator. figure 21-2 recommend layout of oscillator pcb circuit x out x in v ss recommend c1,c2 = 20pf c1 c2 x out x in external clock open x out x in external oscillator rc oscillator (mask option) crystal or ceramic oscillator sx out sx in v ss recommend c1,c2 = 30pf5pf c1 c2 32.768khz 4.19mhz crystal oscillator ceramic resonator c1,c2 = 30pf refer to ac characteristics for selection r value, r ext r r= 47k w 5k w x out x in
gms81c7008/7016 86 apr., 2001 ver 2.01 22. reset the gms81c7008/16 has two types of reset generation proce- dures; one is an external reset input, the other is a watch-dog tim- er reset. table 22-1 shows on-chip hardware initialization by reset action. figure 22-1 simple power-on-reset circuit. 22.1 external reset input the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomplished by holding the reset pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initial- ized. after reset, 64ms (at 4 mhz) add with 7 oscillator periods are required to start execution as shown in figure 22-2. internal ram is not affected by reset. when v dd is turned on, the ram content is indeterminate. therefore, this ram should be initialized before read or tested it. when the reset pin input goes to high, the reset operation is re- leased and the program execution starts at the vector address stored at addresses fffe h - ffff h . a connection for simple power-on-reset is shown in figure . figure 22-2 timing diagram after reset 22.2 watchdog timer reset refer to 18. lcd driver on page 70. 7036p v cc 10uf + 10k w to the reset pin on-chip hardware initial value program counter (pc) (ffff h ) - (fffe h ) g-flag (g) 0 operation mode main operating mode peripheral clock on watchdog timer disable (because the watch timer is disabled) control registers refer to table 8-1 on page 25 low voltage detector enable table 22-1 initializing internal status by reset action main program oscillator (x in pin) ? ? fffe ffff stabilization time t st = 62.5ms at 4.19mhz reset address data 1 2 3 4 5 6 7 ?? start ? ? ? fe ? adl adh op bus bus reset process step ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t st = x 256 f main ? 1024 1
gms81c7008/7016 apr., 2001 ver 2.01 87 23. power fail processor the gms81c7008/16 has an on-chip low voltage detection cir- cuitry to detect the v dd voltage. a configuration register, lvdr (address 0fb h ), can enable or disable the low voltage detect cir- cuitry. whenever v dd falls close to or below 2.2v, the lvd0 is just set to 1, and if it recovering 3.4v, lvd0 is held to 1. if v dd falls below around 3.4v range, the low voltage situation may reset the mcu or freeze the clock according to setting of bit 5 (lvdm) of lvdr . the bit 4 lvd1 function is same with lvd0 except different voltage level 2.1v. the detection voltage is varied very little. see "7.3 dc electrical characteristics" on page 11 for more detail voltage level. in the in-circuit emulator, power fail function is not implemented and user may not use it. therefore, after completed development of user program, this function may be experimented or evaluated using by otp. when power fail certainly occur the mcu was reset, program no- tify this reset circumstance cause by lvd function. so, does not erase the all ram contents and operates subsequently as shown in figure . figure 23-1 low voltage detector register 76543210 lvde initial value: 00 h address: 0fb h lvdr r/w r/w r/w lvd1 operation mode 0: clock freeze 1: reset enable / disable flag 0: disable 1: enable lvds lvd0 power fail voltage selection 0: 3.4v 1: 2.1v r/w lvdm v dd detection flag 1 0: above 3.4v 1: below 3.4v v dd detection flag 2 0: above 2.1v 1: below 2.1v figure 23-2 example s/w of reset by power fail funtion execution initialize ram data lvd0 =1 no reset vector initialize all ports initialize registers ram clear yes skip the initial routine when the reset cause from power fail.
gms81c7008/7016 88 apr., 2001 ver 2.01 figure 23-3 power fail processor situations internal reset internal reset internal reset v dd v dd v dd lvdv dd max lvdv dd min lvdv dd max lvdv dd min lvdv dd max lvdv dd min 64ms 64ms t <64ms 64ms when lvdm = 1
gms81c7008/7016 apr., 2001 ver 2.01 89 24. development tools 24.1 otp programming the gms87c7016 is otp (one time programmable) type mi- crocontrollers. its internal user memory is constructed with eprom (electrically programmable read only memory). the otp microcontroller is generally used for chip evaluation, first production, small amount production, fast mass production, etc. blank otps internal eprom is filled by 00 h , not ff h . note: in any case, you have to use the *.otp file for pro- gramming, not the *.hex file. after assemble the source program, both otp and hex file are generated by automat- ically. the hex file is used during program emulation on the emulator. how to program to program the otp devices, user should use hei own program- mer. ask to hei sales part for purchasing or more detail. programmer: choice-sigma (single type) choice-gnag4 (4-gang type) socket adapter:87c70xx-64sd (for 64sdip) 87c70xx-64qf (for 64mqfp) the choice-sigma is a hei universal single programmer for all of hei otp devices, also the choice-gang4 can program four otps at once. programming procedure 1. select device gms87c7016 as you want. 2. load the *.otp file from the pc to programmer. the file is composed of motorola-s1 format. 3. set the programming address range as below table. 4. mount the socket adapter on the programmer. 5. set the configuration bytes as your needs. 6. start program/verify. select the option for program lock and rc oscil- lation except the user program memory c000 h ~ffff h , there is config- uration byte (address 707f h ) for the selection of program lock and rc oscillation. the configuration byte of otp is shown as figure 24-1. it could be served when user use the otp program- mer (choice-sigma or choice-gang4). figure 24-1 the otp configuration byte 87c70xx-64sd 87c70xx-64qf 87c71xx-52sd address: 707f h 76543210 otp configuration byte lock rc 0: crystal or resonator 1: external rc oscillator 0: allow code read out 1: not allow code read out lock bit oscillation option
gms81c7008/7016 90 apr., 2001 ver 2.01 24.2 emulator eva. board setting *1' 9&/ 4 9/&'& &% *1' 1 1 & 1 5(0287 + 721(' , *1' 5 69 5 67 5 54 5 56 5 58 5 5: 5 49 5 47 5 45 5 43 5 39 5 37 5 35 5 33 5 65 5 63 .8 9 32:(5 581 6723 6/((3 choice-dr. eva 81c51/81c7x b/d rev 1.1 s/n. --------------- -b86(5% 5(6(7 -b86(5$ 9b86(5 ; 4#+ 26& , ; 5 2 5(6(7 ;287 /&'b9gg 9/&'& 6(* 79 6(* 77 6(* 75 6(* 73 6(* 6; 95(* &20 42 6 69 &20 62 6 67 6(* 65 6(* 63 6(* 5; 6(* 59 6(* 57 6(* 55 6(* 53 6(* 4; 6(* 49 6(* 47 6(* 45 6(* 43 6(* ; 6(* 9 6(* 7 6(* 5 6(* 3 6(* 7: 6(* 78 6(* 76 6(* 74 6(* 6< 6(* 6: &20 3 &20 52 6 68 6(* 66 6(* 64 6(* 5< 6(* 5: 6(* 58 6(* 56 6(* 54 6(* 4< 6(* 4: 6(* 48 6(* 46 6(* 44 6(* < 6(* : 6(* 8 6(* 6 6(* 4 *1' 9&/ 3 9&/ 5 &$ *1' 2 8b567 8b;287 *1' 5 6: 5 68 5 53 5 55 5 57 5 59 5 4: 5 48 5 46 5 44 5 3: 5 38 5 36 5 34 5 66 5 64 .8 9 -b86(5% -b86(5$ 1 2 3 4 5 6 7 8 1 2 on off sw4 sw5 sw2 2 1 on off sw1 6xsso\ #.8 9 #+ pd[ 1#533 p$ , vr1 +5v external oscillator socket
gms81c7008/7016 apr., 2001 ver 2.01 91 dip switch and vr setting before execute the user program, keep in your mind the below configuration dip s/w, vr description on/off setting sw1 - emulator reset switch. reset the emulator. reset the emulator. sw2 1 pod reset pin configuration normally off . eva. chip can be reset by external user target board. on : reset is available by either user target system board or emula- tor reset switch. off : reset the mcu by emulator reset switch. does not work from user target board. 2 pod xout pin configuration normally off . mcu xout pin is disconnected internally in the emulator. some cir- cumstance user may connect this circuit. on : output xout signal off : disconnect circuit sw4 1 2 3 external bias resistors connection must be on position. it serves the external bias resistors. if this switches are turned off, lcd bias voltage does not supplied, floated because there are no inter- nal bias resistors and bias tr. inside the emulator. 4 5 6 lcd voltage doubling circuit. must be off position. it is reserved for the gms81c5108. 7 select the stack page. must be on position. this switch select the stack page 0 (off) or page 1 (on). on : for the 81c7xxx off : for the gms81c5108 8 81cx detect the vdd voltage but emulator can not do because emulator can not operate if v dd is below normal opr. voltage (5v), this switch serves lvd environment through the applying 0v to lvd pin of eva. chip during 5v normal operation. position on during normal opera- tion. on : normal operation off : force to detect the lvd, refer to "23. power fail proces- sor" on page 87. sw2-1 reset pin eva. chip sw2-2 xout pin eva. chip oscillator vcl1 vcl2 bias external resistor eva. chip internal vcl0 v ss v dd adjust contrast sw4-1 sw4-2 sw4-3 0.47uf 3 10k w 3 and capacitor vr1 50k w sw4 sw4-8 v dd eva. chip lvd pin
gms81c7008/7016 92 apr., 2001 ver 2.01 sw5 1 internal power supply to sub-oscillation circuit. must be on position. 2 reserved for other purpose. must be off position. vr1 - adjust the lcd contrast. it supply bias voltage and adjust the vcl2 voltage. adjust the proper position as well as lcd display good. vr2 - reserved for other purpose. dont care. dip s/w, vr description on/off setting vcl1 vcl2 bias external resistor eva. chip internal vcl0 v ss v dd adjust contrast sw4-1 sw4-2 sw4-3 0.47uf 3 10k w 3 and capacitor vr1 50k w
appendix
a. mask order sheet 1. customer information company n ame 2. device information 3. marking specification 4. delivery schedule customer sample date yyyy mm dd risk order yyyy mm dd q u an t i t y hynix confirmat i on app l ication o r der date yyyy mm dd t e l : fax: name & s ignature: package 64sdip 64mqfp 5. rom code v erification v e r ifi c a t i o n d a t e : yyyy mm dd app r oval date: yyyy mm dd please confirm our verification data. i agree with your verification data and confirm you to make mask set. check sum: t e l : fax: name & s i gnature: t e l : fax: name & signature: c 0 00 h e000 h f f ff h .o t p file d ata dfff h mask data internet file name: ( .otp) (please check mark into ) pcs pcs check sum: ( ) customer should write inside thick line box. this box is written after 5. v erification. r c o s c o p t . crystal rc gms 81c 701 6 (1 6k r o m) gm s 8 1c 7008 (8k r o m) rom size 8k 16k y y ww k o r e a customers logo c u stomer l o go is n o t r eq u i r e d . y y ww k o r e a gms81c 7 0 c u stome r s pa r t n um b er i f the cus t omer logo mus t be used i n t he special mark , p l ease submit a clean orig i nal of the logo. 0 8 o r 16 e- m a i l: e - mail: 0 1 - a pr - 2001 mask order & verification sheet gms81c7008 -la GMS81C7016 -la gms81c 7 0 -la lot number hynix ro m code num b e r
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 ii b. instruction b.1 terminology list terminology description a accumulator x x - register y y - register psw program status word #imm 8-bit immediate data dp direct page offset address !abs absolute address [ ] indirect expression { } register indirect expression { }+ register indirect expression, after that, register auto-increment .bit bit position a.bit bit position of accumulator dp.bit bit position of direct page memory m.bit bit position of memory data (000 h ~0fff h ) rel relative addressing data upage u-page (0ff00 h ~0ffff h ) offset address n table call number (0~15) + addition x upper nibble expression in opcode y upper nibble expression in opcode - subtraction multiplication / division ( ) contents expression and or ? exclusive or ~not ? assignment / transfer / shift left ? shift right ? exchange = equal 1 not equal 0 bit position 1 bit position
gms81c71xx lcd mcu appendix iii apr. 2001 ver 2.01 b.2 instruction map low high 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 - set1 dp.bit bbs a.bit,rel bbs dp.bit,rel adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das 111 ei ldm dp,#imm sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xax stop low high 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 110 bcs rel lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa 111 beq rel sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 iv b.3 instruction set arithmetic / logic operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. 2 adc dp 05 2 3 a ? ( a ) + ( m ) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 nv--h-zc 5 adc !abs + y 15 3 5 6 adc [ dp + x ] 16 2 6 7 adc [ dp ] + y 17 2 6 8 adc { x } 14 1 3 9 and #imm 84 2 2 logical and 10 and dp 85 2 3 a ? ( a ) ( m ) 11 and dp + x 86 2 4 12 and !abs 87 3 4 n-----z- 13 and !abs + y 95 3 5 14 and [ dp + x ] 96 2 6 15 and [ dp ] + y 97 2 6 16 and { x } 94 1 3 17 asl a 08 1 2 arithmetic shift left 18 asl dp 09 2 4 n-----zc 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 44 2 2 compare accumulator contents with memory contents ( a ) - ( m ) 22 cmp dp 45 2 3 23 cmp dp + x 46 2 4 24 cmp !abs 47 3 4 n-----zc 25 cmp !abs + y 55 3 5 26 cmp [ dp + x ] 56 2 6 27 cmp [ dp ] + y 57 2 6 28 cmp { x } 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents 30 cmpx dp 6c 2 3 ( x ) - ( m ) n-----zc 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents 33 cmpy dp 8c 2 3 ( y ) - ( m ) n-----zc 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1s complement : ( dp ) ? ~( dp ) n-----z- 36 daa df 1 3 decimal adjust for addition n-----zc 37 das cf 1 3 decimal adjust for subtraction n-----zc 38 dec a a8 1 2 decrement n-----z- 39 dec dp a9 2 4 m ? ( m ) - 1 n-----z- 40 dec dp + x b9 2 5 n-----z- 41 dec !abs b8 3 5 n-----z- 42 dec x af 1 2 n-----z- 43 dec y be 1 2 n-----z- ? ? ? ? ? ? ? ? 76543210 ? 0 ? c
gms81c71xx lcd mcu appendix v apr. 2001 ver 2.01 44 div 9b 1 12 divide : ya / x q: a, r: y nv--h-z- 45 eor #imm a4 2 2 exclusive or 46 eor dp a5 2 3 a ? ( a ) ? ( m ) 47 eor dp + x a6 2 4 48 eor !abs a7 3 4 n-----z- 49 eor !abs + y b5 3 5 50 eor [ dp + x ] b6 2 6 51 eor [ dp ] + y b7 2 6 52 eor { x } b4 1 3 53 inc a 88 1 2 increment n-----zc 54 inc dp 89 2 4 m ? ( m ) + 1 n-----z- 55 inc dp + x 99 2 5 n-----z- 56 inc !abs 98 3 5 n-----z- 57 inc x 8f 1 2 n-----z- 58 inc y 9e 1 2 n-----z- 59 lsr a 48 1 2 logical shift right 60 lsr dp 49 2 4 n-----zc 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y a n-----z- 64 or #imm 64 2 2 logical or 65 or dp 65 2 3 a ? ( a ) ( m ) 66 or dp + x 66 2 4 67 or !abs 67 3 4 n-----z- 68 or !abs + y 75 3 5 69 or [ dp + x ] 76 2 6 70 or [ dp ] + y 77 2 6 71 or { x } 74 1 3 72 rol a 28 1 2 rotate left through carry 73 rol dp 29 2 4 n-----zc 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry 77 ror dp 69 2 4 n-----zc 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 24 2 2 subtract with carry 81 sbc dp 25 2 3 a ? ( a ) - ( m ) - ~( c ) 82 sbc dp + x 26 2 4 83 sbc !abs 27 3 4 nv--hzc 84 sbc !abs + y 35 3 5 85 sbc [ dp + x ] 36 2 6 86 sbc [ dp ] + y 37 2 6 87 sbc { x } 34 1 3 88 tst dp 4c 2 3 test memory contents for negative or zero, ( dp ) - 00 h n-----z- 89 xcn ce 1 5 exchange nibbles within the accumulator a 7 ~a 4 ? a 3 ~a 0 n-----z- no. mnemonic op code byte no cycle no operation flag nvgbhizc ? ? ? ? ? ? ? ? 76543210 0 ? ? c ? ? ? ? ? ? ? ? 76543210 c ? ? ? ? ? ? ? ? 76543210 c
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 vi register / memory operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 lda #imm c4 2 2 load accumulator 2 lda dp c5 2 3 a ? ( m ) 3 lda dp + x c6 2 4 4 lda !abs c7 3 4 5 lda !abs + y d5 3 5 n-----z- 6 lda [ dp + x ] d6 2 6 7 lda [ dp ] + y d7 2 6 8 lda { x } d4 1 3 9 lda { x }+ db 1 4 x- register auto-increment : a ? ( m ) , x ? x + 1 10 ldm dp,#imm e4 3 5 load memory with immediate data : ( m ) ? imm -------- 11 ldx #imm 1e 2 2 load x-register 12 ldx dp cc 2 3 x ? ( m ) n-----z- 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load y-register 16 ldy dp c9 2 3 y ? ( m ) n-----z- 17 ldy dp + x d9 2 4 18 ldy !abs d8 3 4 19 sta dp e5 2 4 store accumulator contents in memory 20 sta dp + x e6 2 5 ( m ) ? a 21 sta !abs e7 3 5 22 sta !abs + y f5 3 6 -------- 23 sta [ dp + x ] f6 2 7 24 sta [ dp ] + y f7 2 7 25 sta { x } f4 1 4 26 sta { x }+ fb 1 4 x- register auto-increment : ( m ) ? a, x ? x + 1 27 stx dp ec 2 4 store x-register contents in memory 28 stx dp + y ed 2 5 ( m ) ? x -------- 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memory 31 sty dp + x f9 2 5 ( m ) ? y -------- 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x ? a n-----z- 34 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n-----z- 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n-----z- 36 txa c8 1 2 transfer x-register contents to accumulator: a ? x n-----z- 37 txsp 8e 1 2 transfer x-register contents to stack-pointer: sp ? x n-----z- 38 tya bf 1 2 transfer y-register contents to accumulator: a ? y n-----z- 39 xax ee 1 4 exchange x-register contents with accumulator :x ? a -------- 40 xay de 1 4 exchange y-register contents with accumulator :y ? a -------- 41 xma dp bc 2 5 exchange memory contents with accumulator 42 xma dp+x ad 2 6 ( m ) ? a n-----z- 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x ? y --------
gms81c71xx lcd mcu appendix vii apr. 2001 ver 2.01 16-bit operation bit manipulation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry ya ? ( ya ) ( dp +1 ) ( dp ) nv--h-zc 2cmpw dp 5d 2 4 compare ya contents with memory pair contents : (ya) - (dp+1)(dp) n-----zc 3decw dp bd 2 6 decrement memory pair ( dp+1)( dp) ? ( dp+1) ( dp) - 1 n-----z- 4 incw dp 9d 2 6 increment memory pair ( dp+1) ( dp) ? ( dp+1) ( dp ) + 1 n-----z- 5 ldya dp 7d 2 5 load ya ya ? ( dp +1 ) ( dp ) n-----z- 6 stya dp dd 2 5 store ya ( dp +1 ) ( dp ) ? ya -------- 7 subw dp 3d 2 5 16-bits subtract without carry ya ? ( ya ) - ( dp +1) ( dp) nv--h-zc no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c-flag : c ? ( c ) ( m .bit ) -------c 2 and1b m.bit 8b 3 4 bit and c-flag and not : c ? ( c ) ~( m .bit ) -------c 3 bit dp 0c 2 4 bit test a with memory : mm----z- 4 bit !abs 1c 3 5 z ? ( a ) ( m ) , n ? ( m 7 ) , v ? ( m 6 ) 5 clr1 dp.bit y1 2 4 clear bit : ( m.bit ) ? 0 -------- 6 clra1 a.bit 2b 2 2 clear a bit : ( a.bit ) ? 0 -------- 7 clrc 20 1 2 clear c-flag : c ? 0 -------0 8 clrg 40 1 2 clear g-flag : g ? 0 --0----- 9 clrv 80 1 2 clear v-flag : v ? 0 -0--0--- 10 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? ( c ) ? ( m .bit ) -------c 11 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? ( c ) ? ~(m .bit) -------c 12 ldc m.bit cb 3 4 load c-flag : c ? ( m .bit ) -------c 13 ldcb m.bit cb 3 4 load c-flag with not : c ? ~( m .bit ) -------c 14 not1 m.bit 4b 3 5 bit complement : ( m .bit ) ? ~( m .bit ) -------- 15 or1 m.bit 6b 3 5 bit or c-flag : c ? ( c ) ( m .bit ) -------c 16 or1b m.bit 6b 3 5 bit or c-flag and not : c ? ( c ) ~( m .bit ) -------c 17 set1 dp.bit x1 2 4 set bit : ( m.bit ) ? 1 -------- 18 seta1 a.bit 0b 2 2 set a bit : ( a.bit ) ? 1 -------- 19 setc a0 1 2 set c-flag : c ? 1 -------1 20 setg c0 1 2 set g-flag : g ? 1 --1----- 21 stc m.bit eb 3 6 store c-flag : ( m .bit ) ? c -------- 22 tclr1 !abs 5c 3 6 test and clear bits with a : a - ( m ) , ( m ) ? ( m ) ~( a ) n-----z- 23 tset1 !abs 3c 3 6 test and set bits with a : a - ( m ) , ( m ) ? ( m ) ( a ) n-----z-
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 viii branch / jump operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 bbc a.bit,rel y2 2 4/6 branch if bit clear : -------- 2 bbc dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ? ( pc ) + rel 3 bbs a.bit,rel x2 2 4/6 branch if bit set : -------- 4 bbs dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ? ( pc ) + rel 5 bcc rel 50 2 2/4 branch if carry bit clear if ( c ) = 0 , then pc ? ( pc ) + rel -------- 6 bcs rel d0 2 2/4 branch if carry bit set if ( c ) = 1 , then pc ? ( pc ) + rel -------- 7 beq rel f0 2 2/4 branch if equal if ( z ) = 1 , then pc ? ( pc ) + rel -------- 8 bmi rel 90 2 2/4 branch if minus if ( n ) = 1 , then pc ? ( pc ) + rel -------- 9 bne rel 70 2 2/4 branch if not equal if ( z ) = 0 , then pc ? ( pc ) + rel -------- 10 bpl rel 10 2 2/4 branch if plus if ( n ) = 0 , then pc ? ( pc ) + rel -------- 11 bra rel 2f 2 4 branch always pc ? ( pc ) + rel -------- 12 bvc rel 30 2 2/4 branch if overflow bit clear if (v) = 0 , then pc ? ( pc) + rel -------- 13 bvs rel b0 2 2/4 branch if overflow bit set if (v) = 1 , then pc ? ( pc ) + rel -------- 14 call !abs 3b 3 8 subroutine call 15 call [dp] 5f 2 8 m( sp) ? ( pc h ), sp ? sp - 1, m(sp) ? (pc l ), sp ? sp - 1, if !abs, pc ? abs ; if [dp], pc l ? ( dp ), pc h ? ( dp+1 ) . -------- 16 cbne dp,rel fd 3 5/7 compare and branch if not equal : -------- 17 cbne dp+x,rel 8d 3 6/8 if ( a ) 1 ( m ) , then pc ? ( pc ) + rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : -------- 19 dbne y,rel 7b 2 4/6 if ( m ) 1 0 , then pc ? ( pc ) + rel. 20 jmp !abs 1b 3 3 unconditional jump 21 jmp [!abs] 1f 3 5 pc ? jump address -------- 22 jmp [dp] 3f 2 4 23 pcall upage 4f 2 6 u-page call m(sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ), sp ? sp - 1, pc l ? ( upage ), pc h ? 0ff h . -------- 24 tcall n na 1 8 table call : (sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ),sp ? sp - 1, pc l ? (table vector l), pc h ? (table vector h) --------
gms81c71xx lcd mcu appendix ix apr. 2001 ver 2.01 control operation & etc. no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 brk 0f 1 8 software interrupt : b ? 1, m(sp) ? (pc h ), sp ? sp-1, m(s) ? (pc l ), sp ? sp - 1, m(sp) ? (psw), sp ? sp -1, pc l ? ( 0ffde h ) , pc h ? ( 0ffdf h ) . ---1-0-- 2 di 60 1 3 disable all interrupts : i ? 0 -----0-- 3 ei e0 1 3 enable all interrupt : i ? 1 -----1-- 4 nop ff 1 2 no operation -------- 5 pop a 0d 1 4 sp ? sp + 1, a ? m( sp ) 6 pop x 2d 1 4 sp ? sp + 1, x ? m( sp ) -------- 7 pop y 4d 1 4 sp ? sp + 1, y ? m( sp ) 8 pop psw 6d 1 4 sp ? sp + 1, psw ? m( sp ) restored 9 push a 0e 1 4 m( sp ) ? a , sp ? sp - 1 10 push x 2e 1 4 m( sp ) ? x , sp ? sp - 1 -------- 11 push y 4e 1 4 m( sp ) ? y , sp ? sp - 1 12 push psw 6e 1 4 m( sp ) ? psw , sp ? sp - 1 13 ret 6f 1 5 return from subroutine sp ? sp +1, pc l ? m( sp ), sp ? sp +1, pc h ? m( sp ) -------- 14 reti 7f 1 6 return from interrupt sp ? sp +1, psw ? m( sp ), sp ? sp + 1, pc l ? m( sp ), sp ? sp + 1, pc h ? m( sp ) restored 15 stop ef 1 3 stop mode ( halt cpu, stop oscillator ) --------
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 x c. software example ;***************************************************************************** ; title: GMS81C7016 (gms800 series) demonstration program * ; company: hynix semiconductor inc. * ; contents: lcd display & dual thermometer * ;***************************************************************************** ; ;******** define i/o port & function register address ********* ; r0 equ 0c0h ;port r0 register r1 equ 0c1h ;port r1 register r2 equ 0c2h ;port r2 register r3 equ 0c3h ;port r3 register r4 equ 0c4h ;port r4 register r5 equ 0c5h ;port r5 register ; r0dd equ 0c8h ;port r0 data i/o direction register r1dd equ 0c9h ;port r1 data i/o direction register r2dd equ 0cah ;port r2 data i/o direction register r3dd equ 0cbh ;port r3 data i/o direction register r4dd equ 0cch ;port r4 data i/o direction register r5dd equ 0cdh ;port r5 data i/o direction register ; r0pu equ 0d0h ;port r0 pull-up selection register r1pu equ 0d1h ;port r1 pull-up selection register r2pu equ 0d2h ;port r2 pull-up selection register r3pu equ 0d3h ;port r3 pull-up selection register ; r0cr equ 0d4h ;port r0 type selection register r1cr equ 0d5h ;port r1 type selection register r2cr equ 0d6h ;port r2 type selection register r3cr equ 0d7h ;port r3 type selection register ; ieds equ 0d8h ;external interrupt edge selection register pmr equ 0d9h ;alternative port mode register ienl equ 0dah ;int. enable register low ienh equ 0dbh ;int. enable register high irql equ 0dch ;int. request flag register low irqh equ 0ddh ;int. request flag register high slpr equ 0deh ;sleep mode register wdtr equ 0dfh ;watchdog timer register tm0 equ 0e0h ;timer 0 mode register tdr0 equ 0e1h ;timer 0 data register tm1 equ 0e2h ;timer 1 mode register tdr1 equ 0e3h ;timer 1 data register t1ppr equ 0e3h ;pwm0 period register t1pdr equ 0e4h ;timer 1 pulse duty register pwm0hr equ 0e5h ;pwm0 high register tm2 equ 0e6h ;timer 2 mode register tdr2 equ 0e7h ;timer 2 data register tm3 equ 0e8h ;timer 3 mode register tdr3 equ 0e9h ;timer 3 data register t3ppr equ 0e9h ;pwm1 period register t3pdr equ 0eah ;timer 3 pulse duty register pwm1hr equ 0ebh ;pwm1 high register adcm equ 0ech ;adc mode register adr equ 0edh ;adc result data register wtmr equ 0efh ;watch timer mode register ksmr equ 0f0h ;key scan mode register lcdm equ 0f1h ;lcd mode register lcdpm equ 0f2h ;lcd port mode register rpr equ 0f3h ;ram paging register bitr equ 0f4h ;basic interval timer data register ckctlr equ 0f4h ;clock control register scmr equ 0f5h ;system clock mode register pfdr equ 0fbh ;power fail detector bur equ 0fdh ;buzzer data register smr equ 0feh ;serial mode register siod equ 0ffh ;serial data buffer register ; ;*********** macro definition ************ ; r_savemacro ;save registers to stacks
gms81c71xx lcd mcu appendix xi apr. 2001 ver 2.01 push a push x push y endm ; r_rstrmacro ;restore register from stacks pop y pop x pop a endm ; ;*********** constant definition *********** ; ; ; ;************************************************************************** ; ram allocation * ;************************************************************************** temp0 ds 1 temp1 ds 1 temp2 ds 1 flag1 ds 1 rpten equ 1,flag1 ;set rpten(repeat key enable) after 1 sec. keyonf equ 2,flag1 ;keyscan actkey equ 3,flag1 ;at once, key valid togmo3 equ 4,flag1 ;mode 3 (port toggle) dual_t equ 5,flag1 ;inside & outside temp. dual display outside equ 6,flag1 ;inside temp or outside temp. flag2 ds 1 f200ms equ 0,flag2 f20ms equ 1,flag2 f_1min equ 2,flag2 ;wtimer lpm equ 3,flag2 ;left time pm flag rpm equ 4,flag2 ;right time pm flag status ds 1 rptkey equ 7,status f_clock equ 6,status f_on equ 0,status dispsign ds 1 dispram ds 1 ;temp. dispram1 ds 4 ;left time, right time ondo ds 2 lhour ds 1 ;left watch count lminute ds 1 rhour ds 1 rminute ds 1 ;right watch count buf. timeset ds 4 ;watch set buffer tsflag ds 1 tslpm equ 0,tsflag ;time set left pm tsrpm equ 1,tsflag ;time set right pm blinkcnt ds 1 ;blink counter 0~250 loop ; newky ds 1 oldky ds 1 portdt ds 1 keynm ds 1 keydt ds 1 totlky ds 1 chatfl ds 1 r0buf ds 1 dgtcnt ds 1 mode ds 1 submode ds 1 bsctime ds 1 tempcnt ds 1 hzcnt ds 1 pwmf ds 1 period equ 0,pwmf ; ;************************************************************************** ; interrupt vector table * ;**************************************************************************
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 xii ; org 0ffe0h dw not_used ; timer-3 dw not_used ; timer-2 dw wtimer ; watch timer dw int_ad ; a/d con. dw not_used ; serial i/o dw not_used ; not used dw not_used ; not used dw not_used ; int.2 dw timer1 ; timer-1 dw timer0 ; timer-0 dw int1 ; int.1 dw int0 ; int.0 dw not_used; watch dog timer dw not_used; bit dw int_key ; key scan dw reset ; reset ; ;************************************************************************** ; main program * ;************************************************************************** ; org 0c000h ;program start address ;org 0e000h ; 8k rom version ; reset: ldm wdtr,#0 ldm rpr,#1 ; clrg ldx #0 ramclr: lda #0 ;ram clear(!0000h->!00bfh) sta {x}+ ;m(x) <- a, then x <- x+1 cmpx #0c0h ;x = #0c0h ? bne ramclr setg ldx #0 ramclr1: lda #0 ;ram clear(!0100h->!011ah) sta {x}+ ;m(x) <- a, then x <- x+1 cmpx #1bh ;x = #01bh ? bne ramclr1 clrg ; ldx #0ffh ;stack pointer initial txsp ;sp. <- #0ffh ; ;******** user ram initialize ********** ; ; ldm mode,#4 ; ldm submode,#1 set1 lpm ;kst pm 12:00 just noon ldm lhour,#12h ldm lminute,#00h ldm rhour,#03h ;utc am 03:00 ldm rminute,#00h set1 outside set1 f_on ;power on ; ;********** port initialize ************ ; ldm lcdpm,#0 ;seg0~seg23 are used ldm r0,#0 ;i/o port data clea ldm r1,#0 ;i/o port data clear ldm r2,#0 ldm r3,#0 ldm r0dd,#1111_0001b ;r05,r06,r07: output for keyscan ldm r1dd,#0000_0000b ldm r2dd,#0000_0000b ;r20~r23: input for keyscan ldm r3dd,#0000_0100b ldm r2pu,#0000_1111b ;r20~r23 pull-up active ; ;***** control register initialize ***** ; ldm ckctlr,#0 ;wake up time = 0.0625 sec ;(1/32768)*8*256 = 0.0625sec ldm tdr0,#249 ;8us x (249+1) = 2ms ldm tm0,#0000_1111b ;8bit timer,8us,start count-up ldm tdr1,#249 ;2us x (249+1) = 500us ldm tm1,#0000_1111b ;timer1(8bit),32us,start count-up ldm tm3,#1010_1011b
gms81c71xx lcd mcu appendix xiii apr. 2001 ver 2.01 ldm t3ppr,#99 ldm t3pdr,#50 ldm pwm1hr,#00h ldm pmr,#80h ldm irqh,#0 ;clear all interrupts requeat flags ldm irql,#0 ldm ienl,#1111_1111b ;int2,adc,wt,t2,t3 ldm ienh,#1111_1111b ;bit,wdt,int0,int1,t0,t1 ldm ieds,#0001_0101b ;external int. falling edge select ldm ksmr,#0000_0001b ;r10 key interrupt ldm wtmr,#48h ;enable wt counter, 2hz, select subclock ldm lcdm,#70h ;clk=fsub/64, 1/4duty, internal bias ldm scmr,#0 ;1/2, main osc. ei ;enable interrupts ; loop: bbc keyonf,exe1 ;test if key is pressed call keydecode clr1 keyonf ;clear key flag exe1: bbc f20ms,next1 clr1 f20ms ; ;*****every 20ms***** ; call modeexe ;setting display memory call mode1exe ;during clock, call mode3exe call lcddgt ;7-segments display call lcddot ;dot display call adcexe ;adc execution call lkeyscan next1: bbc f200ms,eloop clr1 f200ms ; ;*****every 200ms***** ; call wind eloop: bbs f_on,exe2 clr1 r0.7 ;for wake-up by next key clr1 r0.6 ;for wake-up by next key clr1 r0.5 ;for wake-up by next key clr1 r0.4 ;for wake-up by next key stop nop nop if [f_1min] clr1 f_1min call modeexe call lcddgt ;7-segments display call lcddot ;dot display endif call lkeyscan exe2: jmp loop ; ;************************************************************************** ; timer0,interrupt routine(2ms) * ;************************************************************************** ; timer0: r_save ;save registers to stacks clrg call make10ms ;set every 10ms r_rstr ;restore registers from stacks reti ; ;************************************************************************** ; timer1 * ;************************************************************************** ; timer1: r_save clrg r_rstr
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 xiv reti ; ;************************************************************************** ; watch timer 4hz * ;************************************************************************** ; wtimer: r_save clrg not1 r0.0 inc hzcnt lda hzcnt cmp #120 bne wt5 ldm hzcnt,#0 set1 f_1min call inc1min wt5: r_rstr reti ; ;************************************************************************** ; port interrupt * ;************************************************************************** ; int_key: r_save clrg bbs chatfl.7,ik8 bbs f_on,ik8 ldx #3 ldm ksmr,#0 ;make r10 to be normal input ww: ldy #2 ;24ms wait ww2: lda #8 ww3: dec a bne ww3 dec y bne ww2 lda r1 ;read r10 ror a bcs ik8 dec x bne ww ldm scmr,#0 ;main osc. set1 f_on set1 chatfl.7 ldm oldky,#0ch ik8: ldm ksmr,#1 r_rstr reti ; ;************************************************************************** ; external interrupt 0 * ;************************************************************************** ; int0: r_save clrg r_rstr reti ; ;************************************************************************** ; external interrupt 1 * ;************************************************************************** ; int1: clrg reti ; ;************************************************************************** ; adc interrupt * ;************************************************************************** ; int_ad: reti ; ;***********************************************************************
gms81c71xx lcd mcu appendix xv apr. 2001 ver 2.01 ; subject: lcddgt ; lcd 7-seg. digit display (tmep,ltime,rtime * ;*********************************************************************** ; entry: dgtcnt (digit counter) * ; x (start address) * ; output: output seg_port (seg0~seg23) * ; output com_port (com0~com3) * ;*********************************************************************** ; example) _ _ _ _ _ _ _ _ * ; dgtcnt=9 | | | | | | | | * ; x=lminute |---| |---| |---| |---| * ; |___| |___| |___| |___| * ; lminute+1 lminute * ;*********************************************************************** ; lcddgt: ldm dgtcnt,#9 ldx #dispram golcd: lda {x} push x if [dgtcnt.0] ;when digit is even number, and #0f0h ;when digit is odd number, xcn call lcddsp ;higher 4 nibble is displayed pop x else and #0fh ;lower 4 nibble is displayed call lcddsp pop x inc x endif dec dgtcnt bpl golcd ret ; ;********* one digit display ********** ; lcddsp: tay ; ;****** zero surpress to blank ****** ; bne gocont ;if a=0 then surpress lda dgtcnt cmp #9 beq blnk cmp #7 beq blnk cmp #3 beq blnk bra gocont blnk: ldy #0ah ; gocont: lda !font+y ;load font data sta temp0 ;store 7-seg font ldm temp2,#7 ;shift counter initialize ldy dgtcnt ;get offset lcd address for dgtcnt lda #14 mul tay dpl1: lda !fontd0+y ;get lcd ram address tax ;store lcd ram address inc y ;increment pointer lda !fontd0+y ;get bit position sta temp1 ;store bit position ror temp0 bcs dpl3 lda #0ffh ;clear bit display ram rol a dec temp1 bpl $-3 setg and {x} bra dpl5 dpl3: lda #00h ;set bit display ram rol a dec temp1 bpl $-3 setg or {x} dpl5: sta {x}
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 xvi clrg inc y dbne temp2,dpl1 ret fontd0 db 13h,1h,13h,2h,13h,0h,13h,3h,0ch,3h,0ch,2h,0ch,0h ;rminute0 fontd1 db 12h,1h,12h,2h,12h,0h,12h,3h,05h,3h,05h,2h,05h,0h ;rminute1 fontd2 db 06h,1h,06h,2h,06h,0h,06h,3h,01h,3h,01h,2h,01h,0h ;rhour0 fontd3 db 80h,0h,01h,1h,01h,1h,80h,0h,80h,0h,80h,0h,80h,0h ;rhour1 fontd4 db 02h,1h,02h,2h,02h,0h,02h,3h,15h,3h,15h,2h,15h,0h ;lminute0 fontd5 db 09h,1h,15h,1h,09h,0h,09h,3h,16h,0h,16h,1h,09h,2h ;lminute1 fontd6 db 14h,1h,14h,2h,14h,0h,14h,3h,00h,3h,00h,2h,00h,0h ;lhour0 fontd7 db 80h,0h,08h,2h,08h,2h,80h,0h,80h,0h,80h,0h,80h,0h ;lhour1 fontd8 db 0bh,2h,0bh,0h,0bh,3h,0bh,1h,17h,1h,17h,0h,17h,3h ;ondo0 fontd9 db 0fh,2h,0fh,0h,0fh,3h,0fh,1h,10h,1h,10h,0h,10h,3h ;ondo1 ; ;************************************************************************** ; 7-segment pattern data * ; _a_ * ; f | g |b * ; |---| * ; e |___|c * ; d .h * ;************************************************************************** ; segment: hgfe dcba to be displayed digit number font db 0011_1111b ; 0 "0" db 0000_0110b ; 1 db 0101_1011b ; 2 db 0100_1111b ; 3 db 0110_0110b ; 4 db 0110_1101b ; 5 db 0111_1101b ; 6 db 0000_0111b ; 7 db 0111_1111b ; 8 "8" db 0110_1111b ; 9 "9" db 0000_0000b ; a "blank" db 0100_0000b ; b "bar" _lcolon equ 2,116h _rcolon equ 2,10eh _ondo equ 2,107h _c equ 0,111h _ram equ 1,10eh _rpm equ 0,10eh _lam equ 1,108h _lpm equ 3,108h _outside equ 1,104h _inside equ 0,107h _s1 equ 2,10ah _snow equ 3,10ah _save equ 3,104h ; lcddot: setc stc _lcolon stc _s1 stc _ondo stc _c ldcb f_on stc _save ldcb dual_t stc _rcolon ldc lpm stc _lpm ldcb lpm stc _lam if [dual_t]==0 ldc rpm ;am,pm setting stc _rpm ldcb rpm stc _ram else ldcb dual_t ;turn off the am, pm stc _rpm
gms81c71xx lcd mcu appendix xvii apr. 2001 ver 2.01 stc _ram endif ldc outside stc _outside ldcb outside stc _inside ret ; ;*********************************************** ; subject: any execution * ;*********************************************** ; description: every 20ms * ; * ;*********************************************** ; modeexe: if [outside] ldx #0 else ldx #1 endif lda ondo+x ;copy ondo data to dispram sta dispram lda sign+x sta dispsign if [dispsign.0] ;if minus ondo, then "-" display if [dispram] < #10 lda #0b0h or dispram sta dispram clrc stc _snow else setc stc _snow endif else clrc stc _snow endif ldx #3 ;move time_buf. to disp_buf. mx1: lda lhour+x sta dispram1+x dec x bpl mx1 bbc dual_t,mx2 ;if single temp. mode, skip lda #0aah ;make erase disp buf. witch sta dispram1+2 ;will be displayed temp. if [outside] ;if dual temp. mode ldx #1 ;if main=ouside, then select inside else ldx #0 ;if main=inside, then select outside endif lda ondo+x sta dispram1+3 lda sign+x ;get bit0 of sign ror a ;copy sign to carry if c ;if minus ondo, then "-" display if [dispram1+3] < #10 lda #0b0h ;exe) bb-4 or dispram1+3 sta dispram1+3 else ldm dispram1+2,#0abh ;exe) b-14 endif else if [dispram1+3] < #10 lda #0a0h ;exe) bb-4 or dispram1+3 sta dispram1+3 endif
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 xviii endif mx2: ret ; ;*********************************************** ; subject: mode 1 execution * ;*********************************************** ; description: clock set * ; * ;*********************************************** ; mode1exe: lda mode and #0f0h cmp #10h ;if mode=1x bne mb3 ldx #3 mb1: lda timeset+x ;timeset buf. copied to disp buf. sta dispram1+x ;4byte & 2 bit dec x bpl mb1 ldc tslpm stc lpm ldc tsrpm stc rpm ; lda mode cmp #10h ;test if left time set mode ? beq mo10 cmp #11h beq mo11 ;test if right time set mode ? bra mb3 mo10: lda blinkcnt cmp #125 ;if less than 124, off bcs mb3 lda #0aah sta dispram1 sta dispram1+1 mb3: ret mo11: lda blinkcnt cmp #125 ;if less than 124, off bcs mb3 lda #0aah sta dispram1+2 sta dispram1+3 bra mb3 ; ;*********************************************** ; subject: mode 3 execution * ;*********************************************** ; description: all pin goes low and high * ; repeatly every 20ms, rectangle wave output * ; * ;*********************************************** ; mode3exe: lda mode cmp #3 bne mo2 lda submode dec a ;because initial no.=1 rol a ;eight times rol a rol a not1 togmo3 bbc togmo3,mo1 clrc adc #4 ;add offset mo1: tay lda !pport+y and #0001_1111b or r0buf sta r0buf sta r0 lda !pport+1+y sta r1 lda !pport+2+y sta r2
gms81c71xx lcd mcu appendix xix apr. 2001 ver 2.01 lda !pport+3+y sta r3 mo2: ret pport db 00h,00h,00h,00h db 00h,00h,00h,00h db 0ffh,0ffh,0ffh,0ffh db 0ffh,0ffh,0ffh,0ffh db 00h,00h,00h,00h db 0ffh,0ffh,0ffh,0ffh db 00h,00h,00h,00h db 0ffh,00h,0ffh,00h db 00h,0ffh,00h,0ffh db 00h,00h,00h,00h db 00h,0ffh,00h,0ffh db 0ffh,00h,0ffh,00h db 55h,55h,55h,55h db 0aah,0aah,0aah,0aah ; ;*********************************************** ; subject: set falg at every 20ms * ;*********************************************** ; make10ms: setc lda #0 adc bsctime daa sta bsctime bne $+4 set1 f200ms ;set f200ms every 200ms and #0fh bne $+4 set1 f20ms ;set f20ms every 20ms ; inc blinkcnt ;used in mode0(clock set) lda blinkcnt cmp #250 bne mz1 ldm blinkcnt,#0 mz1: ret ; ;*********************************************** ; subject: analog to digital conversion * ;*********************************************** ; it is called in main routine every 20ms adcnt ds 2 adr_avr ds 2 adttl ds 4 adflag ds 1 ad_ch equ 0,adflag sign ds 2 divisor equ 250 ; ; :-------: :-------: ; :adr_avr: :adr_avr: ; : : : : ; :outside: :inside : ; :ch4 : :ch5 : ; :-------: :-------: ; adcexe: if [ad_ch]== 0 ldm adcm,#52h ;ad start ch4 ldx #0 ;set to 0 index pointer else ldm adcm,#56h ;ad start ch5 ldx #1 ;set to 1 index pointer endif ldy #20 ;wait adc end adwait: dec y bbs adcm.0,goget cmpy #0 bne adwait
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 xx goget: clrc ;up8 lo8 lda adr ;adttl2|adttl0 = ch4 data adc adttl+x ;adttl3|adttl1 = ch5 data sta adttl+x lda #0 adc adttl+2+x sta adttl+2+x ; inc adcnt+x lda adcnt+x if a == #divisor ;get average value lda #0 sta adcnt+x ldy adttl+2+x lda adttl+x push x ldx #divisor ;divide by divisor div pop x sta adr_avr+x lda #0 ;clear sum buf. sta adttl+x sta adttl+2+x lda adr_avr+x if a < #65 ;ignore below 65 lda #65 endif if a > #240 ;max. 240 lda #240 endif cmp #181 ;make sign rol sign+x ;copy to minus or plus setc sbc #65 tay lda !adtable1+y sta ondo+x endif not1 ad_ch adcquit: ret ; ; adtable db 50h,49h,49h,48h,48h,47h ; 65~ 70 65->+50c db 47h,46h,46h,45h,45h,44h,44h,43h,43h,42h ; 71~ 80 db 41h,41h,40h,40h,40h,39h,39h,38h,38h,37h ; 81~ 90 83->+40'c db 37h,36h,36h,35h,35h,34h,34h,33h,33h,32h ; 91~100 db 32h,31h,31h,30h,30h,30h,29h,29h,28h,28h ;101~110 105->+30'c db 27h,27h,26h,26h,25h,25h,24h,24h,24h,23h ;111~120 db 23h,22h,22h,22h,21h,21h,20h,20h,20h,20h ;121~130 129->+20'c db 19h,19h,18h,18h,17h,17h,16h,16h,15h,15h ;131~140 db 15h,14h,14h,14h,13h,13h,13h,12h,12h,12h ;141~150 db 11h,11h,11h,10h,10h,10h,09h,09h,09h,08h ;151~160 154->+10'c db 08h,07h,07h,07h,06h,05h,05h,04h,04h,04h ;161~170 db 03h,03h,02h,02h,01h,01h,00h,00h,00h,01h ;171~180 178-> 0'c db 01h,02h,02h,03h,03h,04h,04h,05h,05h,06h ;181~190 db 06h,07h,07h,08h,08h,09h,09h,10h,10h,11h ;191~200 199->-10'c db 11h,12h,12h,13h,13h,14h,15h,15h,16h,17h ;201~210 db 17h,18h,18h,19h,19h,20h,20h,21h,21h,22h ;211~220 217->-20'c db 23h,23h,24h,24h,25h,25h,26h,27h,28h,29h ;221~230 db 30h,31h,32h,33h,34h,35h,36h,37h,38h,39h ;231~240 231->-30'c db 40h,41h,42h adtable1 db 50h,50h,50h,49h,49h,48h ; 65~ 70 65->+50c db 48h,47h,47h,46h,46h,45h,45h,44h,44h,43h ; 71~ 80 db 43h,42h,41h,40h,39h,38h,37h,36h,35h,34h ; 81~ 90 83->+40'c db 35h,35h,34h,34h,33h,33h,32h,32h,31h,31h ; 91~100 db 30h,30h,29h,29h,28h,28h,27h,27h,26h,26h ;101~110 105->+30'c db 26h,25h,25h,25h,24h,24h,24h,23h,23h,23h ;111~120 db 22h,22h,22h,21h,21h,21h,20h,20h,20h,20h ;121~130 129->+20'c db 19h,18h,18h,18h,17h,17h,17h,16h,16h,16h ;131~140 db 15h,15h,15h,14h,14h,14h,13h,13h,13h,12h ;141~150 db 12h,11h,11h,10h,10h,09h,09h,09h,08h,08h ;151~160 154->+10'c db 07h,07h,06h,06h,05h,05h,04h,04h,04h,03h ;161~170 db 03h,03h,02h,02h,02h,01h,01h,01h,00h,00h ;171~180 178-> 0'c db 01h,01h,02h,02h,03h,03h,04h,04h,05h,05h ;181~190 db 06h,06h,07h,07h,08h,08h,09h,09h,10h,10h ;191~200 199->-10'c db 11h,11h,12h,12h,13h,13h,14h,15h,15h,16h ;201~210 db 16h,16h,17h,18h,18h,19h,19h,20h,20h,21h ;211~220 217->-20'c
gms81c71xx lcd mcu appendix xxi apr. 2001 ver 2.01 db 21h,22h,23h,23h,24h,24h,25h,25h,26h,27h ;221~230 db 28h,29h,30h,31h,32h,33h,34h,35h,36h,37h ;231~240 231->-30'c db 38h,39h,40h ; ;*********************************************** ; subject: keydecode * ;*********************************************** ; * ;*********************************************** ; repeat equ #1000_0000b clock equ #0100_0000b pwron equ #0000_0001b keydecode: lda keydt ldy #3 mul tay lda !key+y sta temp0 lda !key+1+y sta temp1 lda !key+2+y sta temp2 call condichk bcc quit jmp [temp0] ; key: dw nokey ;0 db 0 dw nokey ;1 db 0 dw nokey ;2 db 0 dw nokey ;3 db 0 dw nokey ;4 db 0 dw nokey ;5 db 0 dw nokey ;6 db 0 dw downkey ;7 db pwron+repeat dw nokey ;8 db 0 dw dualkey ;9 db pwron dw swapkey ;a db pwron dw nokey ;b db 0 dw powerkey ;c db pwron dw clockkey ;d db pwron+clock dw hourkey ;e db pwron+repeat+clock dw minutekey ;f db pwron+repeat+clock dw nokey ;10 db 0 dw upkey ;11 db pwron+repeat dw nokey ;12 db 0 quit: nokey: ret condichk: lda temp2 or status sbc temp2 beq cdc9 bcs cdc10 cdc9: setc ;pass ret cdc10: clrc ;skip ret ;
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 xxii ;*********************************************************** ; display swap key (temp. display swap) * ;*********************************************************** ; swapkey: not1 outside ret ; ;*********************************************************** ; dual key * ;*********************************************************** ; dualkey: not1 dual_t ret ; ;*********************************************************** ; power key * ;*********************************************************** ; powerkey: clr1 f_on if [f_on] else ldm scmr,#2 clr1 dual_t ldm mode,#0 set1 f20ms endif ret ; ;*********************************************************** ; clock key * ;*********************************************************** ; clockkey: set1 f_clock ldm blinkcnt,#0 lda mode ; 10->11 cmp #10h ; 11->00 bne cl1 ; etc. -> 10 ldm mode,#11h bra quit cl1: cmp #11h bne cl2 ldm mode,#0 clr1 f_clock call setto_cnt ldc tslpm stc lpm ldc tsrpm stc rpm ldm hzcnt,#0 clr1 f_1min bra clq cl2: ldm mode,#10h clr1 dual_t call cntto_set ldc lpm stc tslpm ldc rpm stc tsrpm clq: ret ; setto_cnt: ldx #3 cl11: lda timeset+x sta lhour+x dec x bpl cl11 ret ; cntto_set: ldx #3 cl3: lda lhour+x sta timeset+x dec x bpl cl3 ret ; ;*********************************************************** ; hour/minute key * ;*********************************************************** ; hourkey: lda mode
gms81c71xx lcd mcu appendix xxiii apr. 2001 ver 2.01 and #0f0h cmp #10h bne ho1 ldm blinkcnt,#125 lda mode cmp #10h bne ho2 setc ;if mode=10h, then left time set lda #0 ;inc. left hour 1up adc timeset daa if a==#12h not1 tslpm ;adjust am,pm flag endif if a==#13h lda #1 endif sta timeset ho1: ret ho2: cmp #11h bne ho1 setc ;inc. right hour 1up lda #0 adc timeset+2 daa if a==#12h not1 tsrpm ;adjust am,pm flag endif if a==#13h lda #1 endif sta timeset+2 bra ho1 minutekey: lda mode and #0f0h cmp #10h bne mt3 ldm blinkcnt,#125 ldx #3 lda mode cmp #10h bne mt1 ldx #1 mt1: setc lda #0 adc timeset+x daa cmp #60h bne mt2 lda #0 mt2: sta timeset+x mt3: ret ; ;*********************************************** ; up /down key * ;*********************************************** ; upkey: bbs period,pru lda pwm1hr and #0000_0011b cmp #3 bne upk1 lda t3pdr cmp #0ffh bne upk1 upk0: ret upk1: inc t3pdr bne upk0 inc pwm1hr bra upk0 pru: downkey: bbs period,prd lda pwm1hr and #0000_0011b cmp #0
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 xxiv bne dnk1 lda t3pdr cmp #0 beq upk0 dnk1: dec t3pdr lda t3pdr cmp #0ffh bne dnk2 dec pwm1hr dnk2: ret prd: pwmmode: ; ;*********************************************************** ; plus key * ; * ; when mode=3, press puls key, submode is incresed * ; when mode=3, press minus key, submode is decresed * ; * ;*********************************************************** ; ; ;*********************************************** ; subject: keyscan * ;*********************************************** ; strobe out: r05,r06,r07 * ; read port : r20,r21,r22,r23 * ; * ;*********************************************** ; lkeyscan: bbs keyonf,ks7 ldm keynm,#1 ldm totlky,#0 ldm newky,#0 ldy #3 ;initialize strobe line ks1: cmpy #3 bne $+4 clr1 r0.4 ;output strobe signal cmpy #2 bne $+4 clr1 r0.5 ;output strobe signal cmpy #1 bne $+4 clr1 r0.6 ;output strobe signal cmpy #0 bne $+4 clr1 r0.7 ;output strobe signal ; nop nop lda r2 sta portdt ;read key in port and #0fh cmp #0fh ;if key is pressed ? bne ks2 clrc ;keynm + 4 -> keynm lda #4 adc keynm sta keynm bra ks5 ; ks2: ldx #3 ;initialize shift counter ks3: ror portdt bcs ks4 inc totlky ;if totlky is above 2, then quit lda totlky cmp #20 beq ks7 lda keynm ;keynm -> newky sta newky ks4: inc keynm dec x bpl ks3 ks5: set1 r0.4 set1 r0.5
gms81c71xx lcd mcu appendix xxv apr. 2001 ver 2.01 set1 r0.6 set1 r0.7 dec y ;test next line bpl ks1 lda newky cmp #0 ;when no key is pressed, bne ks8 ;initialize newky,oldky,chatfl ks6: lda newky sta oldky ldm chatfl,#0 clr1 rptkey clr1 actkey clr1 rpten ks7: ret ks8: lda newky cmp oldky bne ks6 bbs chatfl.7,ks10 lda chatfl and #0111_1111b cmp #5 bcc ks9 lda newky sta keydt set1 actkey ks81: ldm chatfl,#80h ;set1 chatfl.7 & set to 0 set1 keyonf bra ks7 ks9: inc chatfl bra ks7 ks10: lda chatfl ;repeat key and #0111_1111b bbs rpten,ks11 cmp #25 bcc ks9 set1 rpten bra ks81 ks11: cmp #3 bcc ks9 bbc actkey,ks7 set1 rptkey bra ks81 ; ;*********************************************** ; subject: increase 1 minute * ;*********************************************** ; inc1min: ldx #lminute call min1up ldx #rminute call min1up ret ; min1up: setc lda #0 ; lminute <- lminute + 1 adc {x} daa if a ==#60h setc lda #0 endif sta {x} bcc inc1 dec x lda #0 adc {x} daa if a==#12h if x==#lhour not1 lpm else not1 rpm endif endif if a==#13h lda #1 endif sta {x} inc1: ret
gms81c71xx lcd mcu appendix apr. 2001 ver 2.01 xxvi ; ;*********************************************** ; subject: wind display * ;*********************************************** ; wind: lda tempcnt clrc stc 10dh.0 stc 10dh.1 stc 10dh.2 stc 10dh.3 cmp #0 beq lll3 cmp #1 beq lll2 cmp #2 beq lll1 cmp #3 beq lll0 cmp #4 beq lll1 cmp #5 beq lll2 cmp #6 beq lll3 cmp #7 beq lll4 lll0: stc 10dh.1 lll1: stc 10dh.2 lll2: stc 10dh.3 lll3: stc 10dh.0 lll4: stc 111h.1 inc tempcnt if [tempcnt]==#8 ldm tempcnt,#0 endif ret ; ; ;************************************************************************** ; not_used: nop ;discard unexpected interrupts reti ; end ;notice program end

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